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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-16 04:08:25 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-16 04:08:25 +0000 |
| commit | 2006f936efd6e3a0e982d8171e2af86f36995cf6 (patch) | |
| tree | c233209670d646b1cc4c3255da084153c0641d55 /llvm | |
| parent | f2669eebd554c71fdb8fa609506c61fc3644224c (diff) | |
| download | bcm5719-llvm-2006f936efd6e3a0e982d8171e2af86f36995cf6.tar.gz bcm5719-llvm-2006f936efd6e3a0e982d8171e2af86f36995cf6.zip | |
Fix missing const
llvm-svn: 360849
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/include/llvm/CodeGen/MachineInstrBuilder.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h index 1dcdf086c85..d33e0aa2ab2 100644 --- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h @@ -82,7 +82,7 @@ public: /// Get the register for the operand index. /// The operand at the index should be a register (asserted by /// MachineOperand). - unsigned getReg(unsigned Idx) { return MI->getOperand(Idx).getReg(); } + unsigned getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); } /// Add a new virtual register operand. const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0, |
