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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-02 16:55:33 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-02 16:55:33 +0000 |
| commit | 1c1aab99aeb8170471589538e8faa1bc39e379e2 (patch) | |
| tree | 3045ca68ce17382a4020c7f1e8c26b7337345b77 /llvm | |
| parent | ef8db767d735a215831ef1c7a3ad12e1ba07aad1 (diff) | |
| download | bcm5719-llvm-1c1aab99aeb8170471589538e8faa1bc39e379e2.tar.gz bcm5719-llvm-1c1aab99aeb8170471589538e8faa1bc39e379e2.zip | |
AMDGPU/GlobalISel: InstrMapping for G_TRUNC
llvm-svn: 326588
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir | 31 |
2 files changed, 41 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 3cafc0aa7d8..92a9a3a1783 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -314,6 +314,16 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size); break; } + case AMDGPU::G_TRUNC: { + unsigned Dst = MI.getOperand(0).getReg(); + unsigned Src = MI.getOperand(1).getReg(); + unsigned Bank = getRegBankID(Src, MRI, *TRI); + unsigned DstSize = getSizeInBits(Dst, MRI, *TRI); + unsigned SrcSize = getSizeInBits(Src, MRI, *TRI); + OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize); + OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize); + break; + } case AMDGPU::G_FCMP: { unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir new file mode 100644 index 00000000000..e9a73e01600 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: trunc_i64_to_i32_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1 + ; CHECK-LABEL: name: trunc_i64_to_i32_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s32) = G_TRUNC [[COPY]](s32) + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_TRUNC %0 +... + +--- +name: trunc_i64_to_i32_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1 + ; CHECK-LABEL: name: trunc_i64_to_i32_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s32) = G_TRUNC [[COPY]](s32) + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_TRUNC %0 +... |
