Revert r118457 and r118458. These won't hold for GPRs.

llvm-svn: 118462

2 files changed, 8 insertions, 6 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 0a988138a92..7c7257900fd 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -278,7 +278,6 @@ def brtarget : Operand<OtherVT>;
 
 // A list of registers separated by comma. Used by load/store multiple.
 def reglist : Operand<i32> {
-  int NumOperands = 2;
   string EncoderMethod = "getRegisterListOpValue";
   let PrintMethod = "printRegisterList";
 }
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
index fe6bd34a2b6..296a5c9ce36 100644
--- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -378,11 +378,14 @@ getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
 
 unsigned ARMMCCodeEmitter::
 getRegisterListOpValue(const MCInst &MI, unsigned Op,
-                       SmallVectorImpl<MCFixup> &) const {
-  // {12-8} = Rd
-  // {7-0}  = count
-  unsigned Binary = getARMRegisterNumbering(MI.getOperand(Op).getReg()) << 8;
-  Binary |= MI.getOperand(Op + 1).getImm() & 0xFF;
+                       SmallVectorImpl<MCFixup> &Fixups) const {
+  // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
+  // register in the list, set the corresponding bit.
+  unsigned Binary = 0;
+  for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
+    unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
+    Binary |= 1 << regno;
+  }
   return Binary;
 }