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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-05-23 18:26:42 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-05-23 18:26:42 +0000 |
| commit | 1b086cbcb8888dd00c024f3e4d0d3ebb9aae8dce (patch) | |
| tree | cc3075fdc462e4dc572c58c91ec72b521701b32e /llvm | |
| parent | b7e7a389291839aae07c1946618ba47302b23f09 (diff) | |
| download | bcm5719-llvm-1b086cbcb8888dd00c024f3e4d0d3ebb9aae8dce.tar.gz bcm5719-llvm-1b086cbcb8888dd00c024f3e4d0d3ebb9aae8dce.zip | |
R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg
Patch by: Vincent Lejeune
https://bugs.freedesktop.org/show_bug.cgi?id=64877
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182600
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/vtx-schedule.ll | 22 |
2 files changed, 31 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp index d447f0842d7..832c375bf5b 100644 --- a/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp +++ b/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp @@ -117,8 +117,15 @@ private: const MachineOperand &MO = *I; if (!MO.isReg()) continue; - if (MO.isDef()) - DstMI = MO.getReg(); + if (MO.isDef()) { + unsigned Reg = MO.getReg(); + if (AMDGPU::R600_Reg128RegClass.contains(Reg)) + DstMI = Reg; + else + DstMI = TRI.getMatchingSuperReg(Reg, + TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)), + &AMDGPU::R600_Reg128RegClass); + } if (MO.isUse()) { unsigned Reg = MO.getReg(); if (AMDGPU::R600_Reg128RegClass.contains(Reg)) diff --git a/llvm/test/CodeGen/R600/vtx-schedule.ll b/llvm/test/CodeGen/R600/vtx-schedule.ll new file mode 100644 index 00000000000..a0c79e36d3c --- /dev/null +++ b/llvm/test/CodeGen/R600/vtx-schedule.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; This test is for a scheduler bug where VTX_READ instructions that used +; the result of another VTX_READ instruction were being grouped in the +; same fetch clasue. + +; CHECK: @test +; CHECK: Fetch clause +; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 40 +; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 44 +; CHECK: Fetch clause +; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0 +; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0 +define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in0, i32 addrspace(1)* nocapture %in1) { +entry: + %0 = load i32 addrspace(1)* %in0, align 4 + %1 = load i32 addrspace(1)* %in1, align 4 + %cmp.i = icmp slt i32 %0, %1 + %cond.i = select i1 %cmp.i, i32 %0, i32 %1 + store i32 %cond.i, i32 addrspace(1)* %out, align 4 + ret void +} |
