diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2018-06-20 12:54:02 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-06-20 12:54:02 +0000 |
| commit | 18b9bd7d6c84179f6f91104111c5b743e295499f (patch) | |
| tree | 774c38c906aaf8dee7409f04c8601645dae0d472 /llvm | |
| parent | 644a81953417eaf0176c11927c880309dd73c486 (diff) | |
| download | bcm5719-llvm-18b9bd7d6c84179f6f91104111c5b743e295499f.tar.gz bcm5719-llvm-18b9bd7d6c84179f6f91104111c5b743e295499f.zip | |
[RISCV] Add InstAlias definitions for sgt and sgtu
These are produced by GCC and supported by GAS, but not currently contained in
the pseudoinstruction listing in the RISC-V ISA manual.
llvm-svn: 335120
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.td | 5 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rvi-aliases-valid.s | 7 |
2 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 71e058f1958..e1c3a06fc7a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -478,6 +478,11 @@ def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>; def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>; def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>; +// sgt/sgtu are recognised by the GNU assembler but the canonical slt/sltu +// form will always be printed. Therefore, set a zero weight. +def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>; +def : InstAlias<"sgtu $rd, $rs, $rt", (SLTU GPR:$rd, GPR:$rt, GPR:$rs), 0>; + def : InstAlias<"beqz $rs, $offset", (BEQ GPR:$rs, X0, simm13_lsb0:$offset)>; def : InstAlias<"bnez $rs, $offset", diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s index 2344eb17e3a..eafa486a8fa 100644 --- a/llvm/test/MC/RISCV/rvi-aliases-valid.s +++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s @@ -54,6 +54,13 @@ sltz x31, x1 # CHECK-ALIAS: sgtz t6, ra sgtz x31, x1 +# CHECK-INST: slt ra, gp, sp +# CHECK-ALIAS: slt ra, gp, sp +sgt x1, x2, x3 +# CHECK-INST: sltu tp, t1, t0 +# CHECK-ALIAS: sltu tp, t1, t0 +sgtu x4, x5, x6 + # CHECK-INST: beq a0, zero, 512 # CHECK-ALIAS: beqz a0, 512 beqz x10, 512 |
