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| author | Zhongxing Xu <xuzhongxing@gmail.com> | 2010-05-17 09:47:55 +0000 |
|---|---|---|
| committer | Zhongxing Xu <xuzhongxing@gmail.com> | 2010-05-17 09:47:55 +0000 |
| commit | 188855abef155f566d768859970312d7e09b339d (patch) | |
| tree | a35a279cc10a3585765b724f810bb280143c4eb6 /llvm | |
| parent | 7d22a81b61ca7967b4c9f9654ecc3f06a8f3028c (diff) | |
| download | bcm5719-llvm-188855abef155f566d768859970312d7e09b339d.tar.gz bcm5719-llvm-188855abef155f566d768859970312d7e09b339d.zip | |
Remove unused member variable.
llvm-svn: 103936
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/include/llvm/CodeGen/ScheduleDAG.h | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/ScheduleDAG.cpp | 1 |
2 files changed, 0 insertions, 3 deletions
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h index 7c025e3acbe..67af16545ac 100644 --- a/llvm/include/llvm/CodeGen/ScheduleDAG.h +++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h @@ -34,7 +34,6 @@ namespace llvm { class SDNode; class TargetInstrInfo; class TargetInstrDesc; - class TargetLowering; class TargetMachine; class TargetRegisterClass; template<class Graph> class GraphWriter; @@ -456,7 +455,6 @@ namespace llvm { const TargetMachine &TM; // Target processor const TargetInstrInfo *TII; // Target instruction information const TargetRegisterInfo *TRI; // Target processor register info - const TargetLowering *TLI; // Target lowering info MachineFunction &MF; // Machine function MachineRegisterInfo &MRI; // Virtual/real register map std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp index 587f001cc7b..da20c12c360 100644 --- a/llvm/lib/CodeGen/ScheduleDAG.cpp +++ b/llvm/lib/CodeGen/ScheduleDAG.cpp @@ -27,7 +27,6 @@ ScheduleDAG::ScheduleDAG(MachineFunction &mf) : TM(mf.getTarget()), TII(TM.getInstrInfo()), TRI(TM.getRegisterInfo()), - TLI(TM.getTargetLowering()), MF(mf), MRI(mf.getRegInfo()), EntrySU(), ExitSU() { } |

