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| author | Anders Carlsson <andersca@mac.com> | 2008-10-07 16:14:11 +0000 |
|---|---|---|
| committer | Anders Carlsson <andersca@mac.com> | 2008-10-07 16:14:11 +0000 |
| commit | 1699ad9030da103e91d1db13b9c1f05980baea1f (patch) | |
| tree | de5993108007363e9f82dcaf645971145e2ca242 /llvm | |
| parent | 9a04782fda73c5e8c4ecc586a2ffc601a4cf6fbc (diff) | |
| download | bcm5719-llvm-1699ad9030da103e91d1db13b9c1f05980baea1f.tar.gz bcm5719-llvm-1699ad9030da103e91d1db13b9c1f05980baea1f.zip | |
Certain patterns involving the "movss" instruction were marked as requiring SSE2, when in reality movss is an SSE1 instruction.
llvm-svn: 57246
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/2008-10-07-SSEISelBug.ll | 22 |
2 files changed, 25 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 93f722332bd..35348b69f93 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -2891,11 +2891,11 @@ let AddedComplexity = 15 in { def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))), (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>; def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))), - (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>; + (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>; def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), - (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>; + (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>; def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), - (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>; + (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>; } // Splat v2f64 / v2i64 diff --git a/llvm/test/CodeGen/X86/2008-10-07-SSEISelBug.ll b/llvm/test/CodeGen/X86/2008-10-07-SSEISelBug.ll new file mode 100644 index 00000000000..48089861bc3 --- /dev/null +++ b/llvm/test/CodeGen/X86/2008-10-07-SSEISelBug.ll @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2 + +define <4 x float> @f(float %w) nounwind { +entry: + %retval = alloca <4 x float> ; <<4 x float>*> [#uses=2] + %w.addr = alloca float ; <float*> [#uses=2] + %.compoundliteral = alloca <4 x float> ; <<4 x float>*> [#uses=2] + store float %w, float* %w.addr + %tmp = load float* %w.addr ; <float> [#uses=1] + %0 = insertelement <4 x float> undef, float %tmp, i32 0 ; <<4 x float>> [#uses=1] + %1 = insertelement <4 x float> %0, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1] + %2 = insertelement <4 x float> %1, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1] + %3 = insertelement <4 x float> %2, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1] + store <4 x float> %3, <4 x float>* %.compoundliteral + %tmp1 = load <4 x float>* %.compoundliteral ; <<4 x float>> [#uses=1] + store <4 x float> %tmp1, <4 x float>* %retval + br label %return + +return: ; preds = %entry + %4 = load <4 x float>* %retval ; <<4 x float>> [#uses=1] + ret <4 x float> %4 +} |
