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authorColin LeMahieu <colinl@codeaurora.org>2015-11-03 00:21:19 +0000
committerColin LeMahieu <colinl@codeaurora.org>2015-11-03 00:21:19 +0000
commit160f73e36ff1ba9cf854f68f1f7e2bd80dfe3ec2 (patch)
treefda7a0c30517e94fd8b99a9b865b743be8479712 /llvm
parentc7ed52f2ba04d7e9588f9eb7cda023d8321a07f1 (diff)
downloadbcm5719-llvm-160f73e36ff1ba9cf854f68f1f7e2bd80dfe3ec2.tar.gz
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[Hexagon] Fixing mistaken case fallthrough.
llvm-svn: 251867
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index 8f9d03f344b..ef1887756ac 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -1054,6 +1054,7 @@ static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) {
operand = getDRegFromSubinstEncoding(inst & 0x7);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
+ break;
case Hexagon::V4_SS2_storeh_io:
// Rs 7-4, u 10-8{3_1}, Rt 3-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
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