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| author | Chris Lattner <sabre@nondot.org> | 2006-04-17 21:19:12 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-04-17 21:19:12 +0000 |
| commit | 14c4972b6dfa4e325ec85aa37d72ae36eb13ead3 (patch) | |
| tree | 43238dfe11bb675c03382b94ed50c9a42833f374 /llvm | |
| parent | 6df094b4ab3d7097abeaca42f7c8d29addb8509a (diff) | |
| download | bcm5719-llvm-14c4972b6dfa4e325ec85aa37d72ae36eb13ead3.tar.gz bcm5719-llvm-14c4972b6dfa4e325ec85aa37d72ae36eb13ead3.zip | |
Prefer to allocate V2-V5 before V0,V1. This lets us generate code like this:
vspltisw v2, -12
vrlw v2, v2, v2
instead of:
vspltisw v0, -12
vrlw v2, v0, v0
when a function is returning a value.
llvm-svn: 27771
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 4f56cf74e54..9cd21452268 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -260,7 +260,7 @@ def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, - [V0, V1, V2, V3, V4, V5, + [V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>; |
