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authorAnton Korobeynikov <asl@math.spbu.ru>2009-07-16 13:55:26 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2009-07-16 13:55:26 +0000
commit12996eabbdd7fbbd1338d5fbb81e1213458610fd (patch)
treecec15b46db08ea9207fd089f8cc435d218204579 /llvm
parent590f99b18b2a70079fc65520c8316f0048107259 (diff)
downloadbcm5719-llvm-12996eabbdd7fbbd1338d5fbb81e1213458610fd.tar.gz
bcm5719-llvm-12996eabbdd7fbbd1338d5fbb81e1213458610fd.zip
Let RegisterInfo decide whether it can emit cross-class copy or not
llvm-svn: 75955
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/CodeGen/LowerSubregs.cpp9
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/LowerSubregs.cpp b/llvm/lib/CodeGen/LowerSubregs.cpp
index 14acb71eeb4..5008f1472d3 100644
--- a/llvm/lib/CodeGen/LowerSubregs.cpp
+++ b/llvm/lib/CodeGen/LowerSubregs.cpp
@@ -132,10 +132,11 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
}
} else {
// Insert copy
- const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg);
- assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
- "Extract subreg and Dst must be of same register class");
- TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
+ const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg);
+ const TargetRegisterClass *TRCD = TRI.getPhysicalRegisterRegClass(SrcReg);
+ bool Emitted = TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
+ (void)Emitted;
+ assert(Emitted && "Subreg and Dst must be of compatible register class");
// Transfer the kill/dead flags, if needed.
if (MI->getOperand(0).isDead())
TransferDeadFlag(MI, DstReg, TRI);
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