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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-12-03 05:22:39 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-12-03 05:22:39 +0000 |
| commit | 120a0c92f4805c3b2f0a389d836ecba61c023cd8 (patch) | |
| tree | 3292b91bc43630a6da21fbcc4c56d8e844da911f /llvm | |
| parent | 88652a009bce5ed91645261f5ae6fef3451e4f50 (diff) | |
| download | bcm5719-llvm-120a0c92f4805c3b2f0a389d836ecba61c023cd8.tar.gz bcm5719-llvm-120a0c92f4805c3b2f0a389d836ecba61c023cd8.zip | |
R600/SI: Fix SIFixSGPRCopies for copies to physical registers
This shows up when operands required to be passed in VCC are copied
to.
llvm-svn: 223208
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/SIFixSGPRCopies.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp index 82969f682b5..c7e008a8e5a 100644 --- a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp @@ -182,7 +182,12 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy, unsigned DstReg = Copy.getOperand(0).getReg(); unsigned SrcReg = Copy.getOperand(1).getReg(); unsigned SrcSubReg = Copy.getOperand(1).getSubReg(); - const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); + + const TargetRegisterClass *DstRC + = TargetRegisterInfo::isVirtualRegister(DstReg) ? + MRI.getRegClass(DstReg) : + TRI->getRegClass(DstReg); + const TargetRegisterClass *SrcRC; if (!TargetRegisterInfo::isVirtualRegister(SrcReg) || |
