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authorAkira Hatanaka <ahatanaka@apple.com>2014-12-01 06:14:52 +0000
committerAkira Hatanaka <ahatanaka@apple.com>2014-12-01 06:14:52 +0000
commit107d13c228687ff40d84172764c5082ea90b7fe1 (patch)
treeb1f2b96655665050a57318415739a39a47e200d4 /llvm
parentb9991a265642cea3c544fe407cbb5eb300582f43 (diff)
downloadbcm5719-llvm-107d13c228687ff40d84172764c5082ea90b7fe1.tar.gz
bcm5719-llvm-107d13c228687ff40d84172764c5082ea90b7fe1.zip
Fix capitalization. NFC.
llvm-svn: 222988
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
index 1dc506a7f7f..0c0801d5232 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
@@ -248,9 +248,9 @@ static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize,
}
// Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
- // to our target value, where i is the number of RORs to go the opposite
+ // to our target value, where I is the number of RORs to go the opposite
// direction.
- assert(Size > I && "I should be smaller than element Size");
+ assert(Size > I && "I should be smaller than element size");
unsigned Immr = (Size - I) & (Size - 1);
// If size has a 1 in the n'th bit, create a value that has zeroes in
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