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| author | Simon Dardis <simon.dardis@mips.com> | 2018-04-25 14:12:57 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-04-25 14:12:57 +0000 |
| commit | 0f2f5976d07f4cfc312f2f2485e982551d6d6cf1 (patch) | |
| tree | c68e363623af75422eabff0d58d23f6d7f9fe83d /llvm | |
| parent | 9061e4f48627f01316ddc5887f3dd23225fdd500 (diff) | |
| download | bcm5719-llvm-0f2f5976d07f4cfc312f2f2485e982551d6d6cf1.tar.gz bcm5719-llvm-0f2f5976d07f4cfc312f2f2485e982551d6d6cf1.zip | |
[mips] Teach the delay slot filler to transform 'jal' for microMIPS
ISel is currently picking 'JAL' over 'JAL_MM' for calling a function when
targeting microMIPS. A later patch will correct this behaviour.
This patch extends the mechanism for transforming instructions into their short
delay to recognise 'JAL_MM' for transforming into 'JALS_MM'.
llvm-svn: 330825
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir | 70 |
2 files changed, 71 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp index b12c7e7760a..4f292e66ce0 100644 --- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -575,6 +575,7 @@ static int getEquivalentCallShort(int Opcode) { case Mips::BLTZAL: return Mips::BLTZALS_MM; case Mips::JAL: + case Mips::JAL_MM: return Mips::JALS_MM; case Mips::JALR: return Mips::JALRS_MM; diff --git a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir new file mode 100644 index 00000000000..89f20a5d906 --- /dev/null +++ b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir @@ -0,0 +1,70 @@ +# RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips %s -o - \ +# RUN: -start-after=block-placement | FileCheck %s + +# Test that the micromips jal instruction is correctly handled by the delay slot +# filler by converting it to a short delay slot for the li instruction. + +# CHECK-LABEL: caller13 +# CHECK: jals callee13 +# CHECK-NEXT: li16 + +--- | + declare i32 @callee13(i32, i32) + + define i32 @caller13() { + entry: + %call = tail call i32 (i32, i32) @callee13(i32 1, i32 2) + ret i32 %call + } + +... +--- +name: caller13 +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: +liveins: +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 24 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + stackProtector: '' + maxCallFrameSize: 16 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: + - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true, + di-variable: '', di-expression: '', di-location: '' } +constants: +body: | + bb.0.entry: + liveins: $ra + + $sp = ADDiu $sp, -24 + CFI_INSTRUCTION def_cfa_offset 24 + SW killed $ra, $sp, 20 :: (store 4 into %stack.0) + CFI_INSTRUCTION offset $ra_64, -4 + $a0 = LI16_MM 1 + $a1 = LI16_MM 2 + JAL_MM @callee13, csr_o32, implicit-def dead $ra, implicit killed $a0, implicit killed $a1, implicit-def $sp, implicit-def $v0 + $ra = LW $sp, 20 :: (load 4 from %stack.0) + $sp = ADDiu $sp, 24 + PseudoReturn undef $ra, implicit $v0 + + +... |

