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| author | Richard Osborne <richard@xmos.com> | 2011-08-01 16:45:59 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2011-08-01 16:45:59 +0000 |
| commit | 0cc000ef29d00d110a9b1d04422e4ef75644d019 (patch) | |
| tree | af1cf7d3185e26670ba50d933e801888e66dcc8e /llvm | |
| parent | 789ee677d9f040af9fcdd9c0d9c9c71a0911acab (diff) | |
| download | bcm5719-llvm-0cc000ef29d00d110a9b1d04422e4ef75644d019.tar.gz bcm5719-llvm-0cc000ef29d00d110a9b1d04422e4ef75644d019.zip | |
Fix crash with varargs function with no named parameters.
llvm-svn: 136623
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/XCore/2011-08-01-VarargsBug.ll | 17 |
2 files changed, 19 insertions, 2 deletions
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index 21a119e376c..d23cfe0b92d 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -1148,10 +1148,10 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, int offset = 0; // Save remaining registers, storing higher register numbers at a higher // address - for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) { + for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { // Create a stack slot int FI = MFI->CreateFixedObject(4, offset, true); - if (i == FirstVAReg) { + if (i == (int)FirstVAReg) { XFI->setVarArgsFrameIndex(FI); } offset -= StackSlotSize; diff --git a/llvm/test/CodeGen/XCore/2011-08-01-VarargsBug.ll b/llvm/test/CodeGen/XCore/2011-08-01-VarargsBug.ll new file mode 100644 index 00000000000..2076057441e --- /dev/null +++ b/llvm/test/CodeGen/XCore/2011-08-01-VarargsBug.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +define void @_Z1fz(...) { +entry: +; CHECK: _Z1fz: +; CHECK: extsp 3 +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: ldaw sp, sp[3] +; CHECK: retsp 0 + ret void +} |
