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| author | Sanjay Patel <spatel@rotateright.com> | 2018-09-19 22:00:56 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-09-19 22:00:56 +0000 |
| commit | 0bda919870c8689ca00885c32d76ec3399df1e0b (patch) | |
| tree | c1ca68ffd5d1886feb55f9fd7fb6aa5256559052 /llvm | |
| parent | fdc0de19cb228bb1768b3dd882e79f8a0c5d6112 (diff) | |
| download | bcm5719-llvm-0bda919870c8689ca00885c32d76ec3399df1e0b.tar.gz bcm5719-llvm-0bda919870c8689ca00885c32d76ec3399df1e0b.zip | |
[x86] add test for 256-bit andn (PR37749); NFC
llvm-svn: 342595
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/test/CodeGen/X86/avx-logic.ll | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/avx-logic.ll b/llvm/test/CodeGen/X86/avx-logic.ll index ff85b17a4fb..24fff08f65e 100644 --- a/llvm/test/CodeGen/X86/avx-logic.ll +++ b/llvm/test/CodeGen/X86/avx-logic.ll @@ -335,6 +335,35 @@ define <8 x i32> @and_disguised_i8_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z ret <8 x i32> %t } +define <8 x i32> @andn_disguised_i8_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) { +; AVX1-LABEL: andn_disguised_i8_elts: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 +; AVX1-NEXT: vpaddd %xmm3, %xmm4, %xmm3 +; AVX1-NEXT: vpaddd %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 +; AVX1-NEXT: vandnps {{.*}}(%rip), %ymm0, %ymm0 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3 +; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; INT256-LABEL: andn_disguised_i8_elts: +; INT256: # %bb.0: +; INT256-NEXT: vpaddd %ymm0, %ymm1, %ymm0 +; INT256-NEXT: vpandn {{.*}}(%rip), %ymm0, %ymm0 +; INT256-NEXT: vpaddd %ymm2, %ymm0, %ymm0 +; INT256-NEXT: retq + %add = add <8 x i32> %y, %x + %neg = and <8 x i32> %add, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255> + %and = xor <8 x i32> %neg, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255> + %add1 = add <8 x i32> %and, %z + ret <8 x i32> %add1 +} + define <8 x i32> @or_disguised_i8_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) { ; AVX1-LABEL: or_disguised_i8_elts: ; AVX1: # %bb.0: |
