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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-06-23 02:05:55 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-06-23 02:05:55 +0000 |
| commit | 0b554ed364981a0b5172a0202ee183ef6fc5ae85 (patch) | |
| tree | 4c8cec6d50d1fc6f81d9cca91405586a0b9ffc66 /llvm | |
| parent | 9d95716c159ca4a07b435ec65943fa475cacc997 (diff) | |
| download | bcm5719-llvm-0b554ed364981a0b5172a0202ee183ef6fc5ae85.tar.gz bcm5719-llvm-0b554ed364981a0b5172a0202ee183ef6fc5ae85.zip | |
AMDGPU: Use getAsInteger instead of atoi
llvm-svn: 240365
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 12d08cf4c7f..c73e4481a71 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2211,8 +2211,9 @@ SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG, std::pair<unsigned, const TargetRegisterClass *> SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, - const std::string &Constraint, + const std::string &Constraint_, MVT VT) const { + StringRef Constraint(Constraint_); if (Constraint == "r") { switch(VT.SimpleTy) { default: llvm_unreachable("Unhandled type for 'r' inline asm constraint"); @@ -2232,8 +2233,9 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, } if (RC) { - unsigned Idx = std::atoi(Constraint.substr(2).c_str()); - if (Idx < RC->getNumRegs()) + uint32_t Idx; + bool Failed = Constraint.substr(2).getAsInteger(10, Idx); + if (!Failed && Idx < RC->getNumRegs()) return std::make_pair(RC->getRegister(Idx), RC); } } |
