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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-03-30 14:48:08 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-03-30 14:48:08 +0000 |
| commit | 073a9d74ca4ee6cbf40dc23982884b2a5640364c (patch) | |
| tree | f5854d68a3b3e0231a4f16cfe23e75c8b0a15cea /llvm | |
| parent | 3f55ad8faea9180b9876e143c4a7319ab372d1f9 (diff) | |
| download | bcm5719-llvm-073a9d74ca4ee6cbf40dc23982884b2a5640364c.tar.gz bcm5719-llvm-073a9d74ca4ee6cbf40dc23982884b2a5640364c.zip | |
[X86][BtVer2] Add missing ReadAfterLd to RM variants of AVX horizontal adds and
most vector logic instructions.
Fixed a few InstRW that forgot to specify a ReadAfterLd for the register input
operand.
llvm-svn: 328867
Diffstat (limited to 'llvm')
4 files changed, 24 insertions, 21 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 2994b31fe66..808750eb08c 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -395,7 +395,8 @@ def JWriteFHAddYLd: SchedWriteRes<[JLAGU, JFPU0, JFPA]> { let Latency = 8; let ResourceCycles = [2, 2, 2]; } -def : InstRW<[JWriteFHAddYLd], (instrs VHADDPDYrm, VHADDPSYrm, VHSUBPDYrm, VHSUBPSYrm)>; +def : InstRW<[JWriteFHAddYLd, ReadAfterLd], (instrs VHADDPDYrm, VHADDPSYrm, + VHSUBPDYrm, VHSUBPSYrm)>; //////////////////////////////////////////////////////////////////////////////// // Carry-less multiplication instructions. @@ -510,10 +511,14 @@ def : InstRW<[JWriteFLogic], (instrs ORPDrr, ORPSrr, VORPDrr, VORPSrr, def JWriteFLogicLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> { let Latency = 6; } -def : InstRW<[JWriteFLogicLd], (instrs ORPDrm, ORPSrm, VORPDrm, VORPSrm, - XORPDrm, XORPSrm, VXORPDrm, VXORPSrm, - ANDPDrm, ANDPSrm, VANDPDrm, VANDPSrm, - ANDNPDrm, ANDNPSrm, VANDNPDrm, VANDNPSrm)>; +def : InstRW<[JWriteFLogicLd, ReadAfterLd], (instrs ORPDrm, ORPSrm, + VORPDrm, VORPSrm, + XORPDrm, XORPSrm, + VXORPDrm, VXORPSrm, + ANDPDrm, ANDPSrm, + VANDPDrm, VANDPSrm, + ANDNPDrm, ANDNPSrm, + VANDNPDrm, VANDNPSrm)>; def JWriteFLogicY: SchedWriteRes<[JFPU01, JFPX]> { let ResourceCycles = [2, 2]; @@ -529,10 +534,10 @@ def JWriteFLogicYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> { let ResourceCycles = [2, 2, 2]; let NumMicroOps = 2; } -def : InstRW<[JWriteFLogicYLd], (instrs VORPDYrm, VORPSYrm, - VXORPDYrm, VXORPSYrm, - VANDPDYrm, VANDPSYrm, - VANDNPDYrm, VANDNPSYrm)>; +def : InstRW<[JWriteFLogicYLd, ReadAfterLd], (instrs VORPDYrm, VORPSYrm, + VXORPDYrm, VXORPSYrm, + VANDPDYrm, VANDPSYrm, + VANDNPDYrm, VANDNPSYrm)>; def JWriteVDPPSY: SchedWriteRes<[JFPU1, JFPM, JFPA]> { let Latency = 12; diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s b/llvm/test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s index 524b078d793..391a4128597 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s @@ -17,7 +17,7 @@ vhaddps (%rdi), %ymm1, %ymm2 # CHECK: Timeline view: -# CHECK-NEXT: 01 -# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER . .. vshufps $0, %xmm0, %xmm1, %xmm1 -# CHECK-NEXT: [0,1] D=eeeeeeeeER vhaddps (%rdi), %ymm1, %ymm2 +# CHECK-NEXT: 0 +# CHECK-NEXT: Index 0123456789 +# CHECK: [0,0] DeER . . vshufps $0, %xmm0, %xmm1, %xmm1 +# CHECK-NEXT: [0,1] DeeeeeeeeER vhaddps (%rdi), %ymm1, %ymm2 diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-1.s b/llvm/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-1.s index ed3cb232f27..9a1d9bdcbeb 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-1.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-1.s @@ -17,7 +17,6 @@ vandps (%rdi), %xmm1, %xmm2 # CHECK: Timeline view: -# CHECK-NEXT: 01 -# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeeeER .. vaddps %xmm0, %xmm0, %xmm1 -# CHECK-NEXT: [0,1] D===eeeeeeER vandps (%rdi), %xmm1, %xmm2 +# CHECK: Index 012345678 +# CHECK: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [0,1] DeeeeeeER vandps (%rdi), %xmm1, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-2.s b/llvm/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-2.s index b6d94d00ac1..6f218f85445 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-2.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-2.s @@ -17,7 +17,6 @@ vandps (%rdi), %ymm1, %ymm2 # CHECK: Timeline view: -# CHECK-NEXT: 01 -# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeeeER .. vaddps %ymm0, %ymm0, %ymm1 -# CHECK-NEXT: [0,1] .D==eeeeeeER vandps (%rdi), %ymm1, %ymm2 +# CHECK: Index 0123456789 +# CHECK: [0,0] DeeeER . vaddps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [0,1] .DeeeeeeER vandps (%rdi), %ymm1, %ymm2 |
