diff options
| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2017-06-30 20:43:40 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2017-06-30 20:43:40 +0000 |
| commit | 03ab2e2b1c85ed25c386b5d4eef707949507b91a (patch) | |
| tree | f14abf6bab159acb7b7eacbc5d459ce61551e640 /llvm | |
| parent | ff5e7e12956705c8f523848485042835fac58eea (diff) | |
| download | bcm5719-llvm-03ab2e2b1c85ed25c386b5d4eef707949507b91a.tar.gz bcm5719-llvm-03ab2e2b1c85ed25c386b5d4eef707949507b91a.zip | |
[SystemZ] Add all remaining instructions
This adds all remaining instructions that were still missing, mostly
privileged and semi-privileged system-level instructions. These are
provided for use with the assembler and disassembler only.
This brings the LLVM assembler / disassembler to parity with the
GNU binutils tools.
llvm-svn: 306876
Diffstat (limited to 'llvm')
24 files changed, 5341 insertions, 135 deletions
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp index ad05779a9f6..ee23692ad1d 100644 --- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -61,6 +61,7 @@ enum RegisterKind { VR64Reg, VR128Reg, AR32Reg, + CR64Reg, }; enum MemoryKind { @@ -343,6 +344,7 @@ public: bool isVF128() const { return false; } bool isVR128() const { return isReg(VR128Reg); } bool isAR32() const { return isReg(AR32Reg); } + bool isCR64() const { return isReg(CR64Reg); } bool isAnyReg() const { return (isReg() || isImm(0, 15)); } bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); } bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); } @@ -379,7 +381,8 @@ private: RegGR, RegFP, RegV, - RegAR + RegAR, + RegCR }; struct Register { RegisterGroup Group; @@ -487,6 +490,9 @@ public: OperandMatchResultTy parseAR32(OperandVector &Operands) { return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg); } + OperandMatchResultTy parseCR64(OperandVector &Operands) { + return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg); + } OperandMatchResultTy parseAnyReg(OperandVector &Operands) { return parseAnyRegister(Operands); } @@ -648,6 +654,8 @@ bool SystemZAsmParser::parseRegister(Register &Reg) { Reg.Group = RegV; else if (Prefix == 'a' && Reg.Num < 16) Reg.Group = RegAR; + else if (Prefix == 'c' && Reg.Num < 16) + Reg.Group = RegCR; else return Error(Reg.StartLoc, "invalid register"); @@ -741,6 +749,10 @@ SystemZAsmParser::parseAnyRegister(OperandVector &Operands) { Kind = AR32Reg; RegNo = SystemZMC::AR32Regs[Reg.Num]; } + else if (Reg.Group == RegCR) { + Kind = CR64Reg; + RegNo = SystemZMC::CR64Regs[Reg.Num]; + } else { return MatchOperand_ParseFail; } @@ -1056,6 +1068,8 @@ bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, RegNo = SystemZMC::VR128Regs[Reg.Num]; else if (Reg.Group == RegAR) RegNo = SystemZMC::AR32Regs[Reg.Num]; + else if (Reg.Group == RegCR) + RegNo = SystemZMC::CR64Regs[Reg.Num]; StartLoc = Reg.StartLoc; EndLoc = Reg.EndLoc; return false; diff --git a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp index 27fd70bc609..8903b57ffd0 100644 --- a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -162,6 +162,12 @@ static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16); } +static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16); +} + template<unsigned N> static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { if (!isUInt<N>(Imm)) diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index dfea7e33fa1..727ab921daf 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -116,6 +116,13 @@ const unsigned SystemZMC::AR32Regs[16] = { SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15 }; +const unsigned SystemZMC::CR64Regs[16] = { + SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3, + SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7, + SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11, + SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15 +}; + unsigned SystemZMC::getFirstReg(unsigned Reg) { static unsigned Map[SystemZ::NUM_TARGET_REGS]; static bool Initialized = false; diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h index d9926c7e498..dbca3485290 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -55,6 +55,7 @@ extern const unsigned VR32Regs[32]; extern const unsigned VR64Regs[32]; extern const unsigned VR128Regs[32]; extern const unsigned AR32Regs[16]; +extern const unsigned CR64Regs[16]; // Return the 0-based number of the first architectural register that // contains the given LLVM register. E.g. R1D -> 1. diff --git a/llvm/lib/Target/SystemZ/SystemZ.td b/llvm/lib/Target/SystemZ/SystemZ.td index c5f324418da..41300a1b629 100644 --- a/llvm/lib/Target/SystemZ/SystemZ.td +++ b/llvm/lib/Target/SystemZ/SystemZ.td @@ -56,6 +56,7 @@ include "SystemZInstrVector.td" include "SystemZInstrFP.td" include "SystemZInstrHFP.td" include "SystemZInstrDFP.td" +include "SystemZInstrSystem.td" def SystemZInstrInfo : InstrInfo {} diff --git a/llvm/lib/Target/SystemZ/SystemZFeatures.td b/llvm/lib/Target/SystemZ/SystemZFeatures.td index ffb0b8d1c86..c5faa0d6288 100644 --- a/llvm/lib/Target/SystemZ/SystemZFeatures.td +++ b/llvm/lib/Target/SystemZ/SystemZFeatures.td @@ -68,11 +68,21 @@ def FeaturePopulationCount : SystemZFeature< "Assume that the population-count facility is installed" >; +def FeatureMessageSecurityAssist3 : SystemZFeature< + "message-security-assist-extension3", "MessageSecurityAssist3", + "Assume that the message-security-assist extension facility 3 is installed" +>; + def FeatureMessageSecurityAssist4 : SystemZFeature< "message-security-assist-extension4", "MessageSecurityAssist4", "Assume that the message-security-assist extension facility 4 is installed" >; +def FeatureResetReferenceBitsMultiple : SystemZFeature< + "reset-reference-bits-multiple", "ResetReferenceBitsMultiple", + "Assume that the reset-reference-bits-multiple facility is installed" +>; + def Arch9NewFeatures : SystemZFeatureList<[ FeatureDistinctOps, FeatureFastSerialization, @@ -81,7 +91,9 @@ def Arch9NewFeatures : SystemZFeatureList<[ FeatureInterlockedAccess1, FeatureLoadStoreOnCond, FeaturePopulationCount, - FeatureMessageSecurityAssist4 + FeatureMessageSecurityAssist3, + FeatureMessageSecurityAssist4, + FeatureResetReferenceBitsMultiple ]>; //===----------------------------------------------------------------------===// @@ -120,13 +132,19 @@ def FeatureDFPZonedConversion : SystemZFeature< "Assume that the DFP zoned-conversion facility is installed" >; +def FeatureEnhancedDAT2 : SystemZFeature< + "enhanced-dat-2", "EnhancedDAT2", + "Assume that the enhanced-DAT facility 2 is installed" +>; + def Arch10NewFeatures : SystemZFeatureList<[ FeatureExecutionHint, FeatureLoadAndTrap, FeatureMiscellaneousExtensions, FeatureProcessorAssist, FeatureTransactionalExecution, - FeatureDFPZonedConversion + FeatureDFPZonedConversion, + FeatureEnhancedDAT2 ]>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index 5f6115ed86a..7620e06ccbc 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -2468,6 +2468,14 @@ class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, let OpType = "reg"; } +class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls> + : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src), + mnemonic#"\t$R1", []> { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; + let R2 = 0; +} + class UnaryMemRRFc<string mnemonic, bits<16> opcode, RegisterOperand cls1, RegisterOperand cls2> : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src), @@ -2702,6 +2710,26 @@ class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode, let AddedComplexity = 7; } +class SideEffectBinaryRRE<string mnemonic, bits<16> opcode, + RegisterOperand cls1, RegisterOperand cls2> + : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), + mnemonic#"\t$R1, $R2", []>; + +class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode, + RegisterOperand cls1, RegisterOperand cls2> + : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2), + mnemonic#"\t$R1, $R2", []> { + let R3 = 0; + let M4 = 0; +} + +class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode, + RegisterOperand cls1, RegisterOperand cls2> + : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2), + mnemonic#"\t$R1, $R2", []> { + let M3 = 0; +} + class SideEffectBinaryIE<string mnemonic, bits<16> opcode, Immediate imm1, Immediate imm2> : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2), @@ -2729,6 +2757,10 @@ class SideEffectBinarySSf<string mnemonic, bits<8> opcode> : InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2), mnemonic##"\t$BD1, $BDL2", []>; +class SideEffectBinarySSE<string mnemonic, bits<16> opcode> + : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2), + mnemonic#"\t$BD1, $BD2", []>; + class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode, RegisterOperand cls1, RegisterOperand cls2> : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src), @@ -3612,6 +3644,22 @@ class SideEffectTernarySSc<string mnemonic, bits<8> opcode> shift12only:$BD2, imm32zx4:$I3), mnemonic##"\t$BDL1, $BD2, $I3", []>; +class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode, + RegisterOperand cls1, RegisterOperand cls2, + RegisterOperand cls3> + : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3), + mnemonic#"\t$R1, $R2, $R3", []> { + let M4 = 0; +} + +class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode, + RegisterOperand cls1, RegisterOperand cls2, + RegisterOperand cls3> + : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3), + mnemonic#"\t$R1, $R3, $R2", []> { + let M4 = 0; +} + class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode, RegisterOperand cls1, RegisterOperand cls2, @@ -3630,6 +3678,13 @@ class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode, : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3), mnemonic#"\t$R1, $R2, $M3", []>; +multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode, + RegisterOperand cls1, + RegisterOperand cls2> { + def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>; + def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>; +} + class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode, RegisterOperand cls1, RegisterOperand cls2, Immediate imm> @@ -3720,6 +3775,18 @@ multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, } } +class SideEffectTernaryRS<string mnemonic, bits<8> opcode, + RegisterOperand cls1, RegisterOperand cls2> + : InstRSa<opcode, (outs), + (ins cls1:$R1, cls2:$R3, bdaddr12only:$BD2), + mnemonic#"\t$R1, $R3, $BD2", []>; + +class SideEffectTernaryRSY<string mnemonic, bits<16> opcode, + RegisterOperand cls1, RegisterOperand cls2> + : InstRSYa<opcode, (outs), + (ins cls1:$R1, cls2:$R3, bdaddr20only:$BD2), + mnemonic#"\t$R1, $R3, $BD2", []>; + class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode, RegisterOperand cls1, RegisterOperand cls2> : InstRSa<opcode, (outs cls1:$R1, cls2:$R3), @@ -3997,6 +4064,35 @@ multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> { VR128:$V4, imm32zx4:$M5, 0)>; } +class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode, + RegisterOperand cls1, RegisterOperand cls2, + RegisterOperand cls3> + : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4), + mnemonic#"\t$R1, $R2, $R3, $M4", []>; + +multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode, + RegisterOperand cls1, + RegisterOperand cls2, + RegisterOperand cls3> { + def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; + def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; + def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>; +} + +class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode, + RegisterOperand cls1, RegisterOperand cls2, + RegisterOperand cls3> + : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4), + mnemonic#"\t$R1, $R3, $R2, $M4", []>; + +multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode, + RegisterOperand cls1, + RegisterOperand cls2, + RegisterOperand cls3> { + def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>; + def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>; +} + class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode, RegisterOperand cls> : InstSSe<opcode, (outs), @@ -4012,6 +4108,16 @@ class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, let mayStore = 1; } +class CmpSwapRRE<string mnemonic, bits<16> opcode, + RegisterOperand cls1, RegisterOperand cls2> + : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), + mnemonic#"\t$R1, $R2", []> { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; + let mayLoad = 1; + let mayStore = 1; +} + class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode = bdaddr12only> : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index 823e125d32a..98f66c29ae6 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1932,54 +1932,12 @@ let mayLoad = 1, Defs = [CC] in let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; -// Supervisor call. -let hasSideEffects = 1, isCall = 1, Defs = [CC] in - def SVC : SideEffectUnaryI<"svc", 0x0A, imm32zx8>; - -// Monitor call. -let hasSideEffects = 1, isCall = 1 in - def MC : SideEffectBinarySI<"mc", 0xAF, imm32zx8>; - -// Store clock. -let hasSideEffects = 1, Defs = [CC] in { - def STCK : StoreInherentS<"stck", 0xB205, null_frag, 8>; - def STCKF : StoreInherentS<"stckf", 0xB27C, null_frag, 8>; - def STCKE : StoreInherentS<"stcke", 0xB278, null_frag, 16>; -} - -// Store facility list. -let hasSideEffects = 1, Uses = [R0D], Defs = [R0D, CC] in - def STFLE : StoreInherentS<"stfle", 0xB2B0, null_frag, 0>; - -// Extract CPU attribute. -let hasSideEffects = 1 in - def ECAG : BinaryRSY<"ecag", 0xEB4C, null_frag, GR64>; - -// Extract CPU time. -let Defs = [R0D, R1D], hasSideEffects = 1, mayLoad = 1 in - def ECTG : SideEffectTernarySSF<"ectg", 0xC81, GR64>; - -// Extract PSW. -let hasSideEffects = 1, Uses = [CC] in - def EPSW : InherentDualRRE<"epsw", 0xB98D, GR32>; - // Execute. let hasSideEffects = 1 in { def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; } -// Program return. -let hasSideEffects = 1, Defs = [CC] in - def PR : SideEffectInherentE<"pr", 0x0101>; - -// Move with key. -let mayLoad = 1, mayStore = 1, Defs = [CC] in - def MVCK : MemoryBinarySSd<"mvck", 0xD9, GR64>; - -// Store real address. -def STRAG : StoreSSE<"strag", 0xE502>; - //===----------------------------------------------------------------------===// // .insn directive instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/SystemZ/SystemZInstrSystem.td b/llvm/lib/Target/SystemZ/SystemZInstrSystem.td new file mode 100644 index 00000000000..a9803c2d83e --- /dev/null +++ b/llvm/lib/Target/SystemZ/SystemZInstrSystem.td @@ -0,0 +1,517 @@ +//==- SystemZInstrSystem.td - SystemZ system instructions -*- tblgen-*-----==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// The instructions in this file implement SystemZ system-level instructions. +// Most of these instructions are privileged or semi-privileged. They are +// not used for code generation, but are provided for use with the assembler +// and disassembler only. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Program-Status Word Instructions. +//===----------------------------------------------------------------------===// + +// Extract PSW. +let hasSideEffects = 1, Uses = [CC] in + def EPSW : InherentDualRRE<"epsw", 0xB98D, GR32>; + +// Load PSW (extended). +let hasSideEffects = 1, Defs = [CC], mayLoad = 1 in { + def LPSW : SideEffectUnaryS<"lpsw", 0x8200, null_frag, 8>; + def LPSWE : SideEffectUnaryS<"lpswe", 0xB2B2, null_frag, 16>; +} + +// Insert PSW key. +let Uses = [R2L], Defs = [R2L] in + def IPK : SideEffectInherentS<"ipk", 0xB20B, null_frag>; + +// Set PSW key from address. +let hasSideEffects = 1 in + def SPKA : SideEffectAddressS<"spka", 0xB20A, null_frag>; + +// Set system mask. +let hasSideEffects = 1, mayLoad = 1 in + def SSM : SideEffectUnaryS<"ssm", 0x8000, null_frag, 1>; + +// Store then AND/OR system mask. +let hasSideEffects = 1 in { + def STNSM : StoreSI<"stnsm", 0xAC, null_frag, imm32zx8>; + def STOSM : StoreSI<"stosm", 0xAD, null_frag, imm32zx8>; +} + +// Insert address space control. +let hasSideEffects = 1 in + def IAC : InherentRRE<"iac", 0xB224, GR32, null_frag>; + +// Set address space control (fast). +let hasSideEffects = 1 in { + def SAC : SideEffectAddressS<"sac", 0xB219, null_frag>; + def SACF : SideEffectAddressS<"sacf", 0xB279, null_frag>; +} + +//===----------------------------------------------------------------------===// +// Control Register Instructions. +//===----------------------------------------------------------------------===// + +// Load control. +def LCTL : LoadMultipleRS<"lctl", 0xB7, CR64>; +def LCTLG : LoadMultipleRSY<"lctlg", 0xEB2F, CR64>; + +// Store control. +def STCTL : StoreMultipleRS<"stctl", 0xB6, CR64>; +def STCTG : StoreMultipleRSY<"stctg", 0xEB25, CR64>; + +// Extract primary ASN (and instance). +let hasSideEffects = 1 in { + def EPAR : InherentRRE<"epar", 0xB226, GR32, null_frag>; + def EPAIR : InherentRRE<"epair", 0xB99A, GR64, null_frag>; +} + +// Extract secondary ASN (and instance). +let hasSideEffects = 1 in { + def ESAR : InherentRRE<"esar", 0xB227, GR32, null_frag>; + def ESAIR : InherentRRE<"esair", 0xB99B, GR64, null_frag>; +} + +// Set secondary ASN (and instance). +let hasSideEffects = 1 in { + def SSAR : SideEffectUnaryRRE<"ssar", 0xB225, GR32, null_frag>; + def SSAIR : SideEffectUnaryRRE<"ssair", 0xB99F, GR64, null_frag>; +} + +// Extract and set extended authority. +let hasSideEffects = 1 in + def ESEA : UnaryTiedRRE<"esea", 0xB99D, GR32>; + +//===----------------------------------------------------------------------===// +// Prefix-Register Instructions. +//===----------------------------------------------------------------------===// + +// Set prefix. +let hasSideEffects = 1 in + def SPX : SideEffectUnaryS<"spx", 0xB210, null_frag, 4>; + +// Store prefix. +let hasSideEffects = 1 in + def STPX : StoreInherentS<"stpx", 0xB211, null_frag, 4>; + +//===----------------------------------------------------------------------===// +// Storage-Key and Real Memory Instructions. +//===----------------------------------------------------------------------===// + +// Insert storage key extended. +let hasSideEffects = 1 in + def ISKE : BinaryRRE<"iske", 0xB229, null_frag, GR32, GR64>; + +// Insert virtual storage key. +let hasSideEffects = 1 in + def IVSK : BinaryRRE<"ivsk", 0xB223, null_frag, GR32, GR64>; + +// Set storage key extended. +let hasSideEffects = 1, Defs = [CC] in + defm SSKE : SideEffectTernaryRRFcOpt<"sske", 0xB22B, GR32, GR64>; + +// Reset reference bit extended. +let hasSideEffects = 1, Defs = [CC] in + def RRBE : SideEffectBinaryRRE<"rrbe", 0xB22A, GR32, GR64>; + +// Reset reference bits multiple. +let Predicates = [FeatureResetReferenceBitsMultiple], hasSideEffects = 1 in + def RRBM : UnaryRRE<"rrbm", 0xB9AE, null_frag, GR64, GR64>; + +// Perform frame management function. +let hasSideEffects = 1 in + def PFMF : SideEffectBinaryMemRRE<"pfmf", 0xB9AF, GR32, GR64>; + +// Test block. +let hasSideEffects = 1, mayStore = 1, Uses = [R0D], Defs = [R0D, CC] in + def TB : SideEffectBinaryRRE<"tb", 0xB22C, GR64, GR64>; + +// Page in / out. +let mayLoad = 1, mayStore = 1, Defs = [CC] in { + def PGIN : SideEffectBinaryRRE<"pgin", 0xB22E, GR64, GR64>; + def PGOUT : SideEffectBinaryRRE<"pgout", 0xB22F, GR64, GR64>; +} + +//===----------------------------------------------------------------------===// +// Dynamic-Address-Translation Instructions. +//===----------------------------------------------------------------------===// + +// Invalidate page table entry. +let hasSideEffects = 1 in + defm IPTE : SideEffectQuaternaryRRFaOptOpt<"ipte", 0xB221, GR64, GR32, GR32>; + +// Invalidate DAT table entry. +let hasSideEffects = 1 in + defm IDTE : SideEffectQuaternaryRRFbOpt<"idte", 0xB98E, GR64, GR64, GR64>; + +// Compare and replace DAT table entry. +let Predicates = [FeatureEnhancedDAT2], hasSideEffects = 1, Defs = [CC] in + defm CRDTE : SideEffectQuaternaryRRFbOpt<"crdte", 0xB98F, GR128, GR128, GR64>; + +// Purge TLB. +let hasSideEffects = 1 in + def PTLB : SideEffectInherentS<"ptlb", 0xB20D, null_frag>; + +// Compare and swap and purge. +let hasSideEffects = 1, Defs = [CC] in { + def CSP : CmpSwapRRE<"csp", 0xB250, GR128, GR64>; + def CSPG : CmpSwapRRE<"cspg", 0xB98A, GR128, GR64>; +} + +// Load page-table-entry address. +let hasSideEffects = 1, Defs = [CC] in + def LPTEA : TernaryRRFb<"lptea", 0xB9AA, GR64, GR64, GR64>; + +// Load real address. +let hasSideEffects = 1, Defs = [CC] in { + defm LRA : LoadAddressRXPair<"lra", 0xB1, 0xE313, null_frag>; + def LRAG : LoadAddressRXY<"lrag", 0xE303, null_frag, laaddr20pair>; +} + +// Store real address. +def STRAG : StoreSSE<"strag", 0xE502>; + +// Load using real address. +let mayLoad = 1 in { + def LURA : UnaryRRE<"lura", 0xB24B, null_frag, GR32, GR64>; + def LURAG : UnaryRRE<"lurag", 0xB905, null_frag, GR64, GR64>; +} + +// Store using real address. +let mayStore = 1 in { + def STURA : SideEffectBinaryRRE<"stura", 0xB246, GR32, GR64>; + def STURG : SideEffectBinaryRRE<"sturg", 0xB925, GR64, GR64>; +} + +// Test protection. +let hasSideEffects = 1, Defs = [CC] in + def TPROT : SideEffectBinarySSE<"tprot", 0xE501>; + +//===----------------------------------------------------------------------===// +// Memory-move Instructions. +//===----------------------------------------------------------------------===// + +// Move with key. +let mayLoad = 1, mayStore = 1, Defs = [CC] in + def MVCK : MemoryBinarySSd<"mvck", 0xD9, GR64>; + +// Move to primary / secondary. +let mayLoad = 1, mayStore = 1, Defs = [CC] in { + def MVCP : MemoryBinarySSd<"mvcp", 0xDA, GR64>; + def MVCS : MemoryBinarySSd<"mvcs", 0xDB, GR64>; +} + +// Move with source / destination key. +let mayLoad = 1, mayStore = 1, Uses = [R0L, R1L] in { + def MVCSK : SideEffectBinarySSE<"mvcsk", 0xE50E>; + def MVCDK : SideEffectBinarySSE<"mvcdk", 0xE50F>; +} + +// Move with optional specifications. +let mayLoad = 1, mayStore = 1, Uses = [R0L] in + def MVCOS : SideEffectTernarySSF<"mvcos", 0xC80, GR64>; + +// Move page. +let mayLoad = 1, mayStore = 1, Uses = [R0L], Defs = [CC] in + def MVPG : SideEffectBinaryRRE<"mvpg", 0xB254, GR64, GR64>; + +//===----------------------------------------------------------------------===// +// Address-Space Instructions. +//===----------------------------------------------------------------------===// + +// Load address space parameters. +let hasSideEffects = 1, Defs = [CC] in + def LASP : SideEffectBinarySSE<"lasp", 0xE500>; + +// Purge ALB. +let hasSideEffects = 1 in + def PALB : SideEffectInherentRRE<"palb", 0xB248>; + +// Program call. +let hasSideEffects = 1 in + def PC : SideEffectAddressS<"pc", 0xB218, null_frag>; + +// Program return. +let hasSideEffects = 1, Defs = [CC] in + def PR : SideEffectInherentE<"pr", 0x0101>; + +// Program transfer (with instance). +let hasSideEffects = 1 in { + def PT : SideEffectBinaryRRE<"pt", 0xB228, GR32, GR64>; + def PTI : SideEffectBinaryRRE<"pti", 0xB99E, GR64, GR64>; +} + +// Resume program. +let hasSideEffects = 1, Defs = [CC] in + def RP : SideEffectAddressS<"rp", 0xB277, null_frag>; + +// Branch in subspace group. +let hasSideEffects = 1 in + def BSG : UnaryRRE<"bsg", 0xB258, null_frag, GR64, GR64>; + +// Branch and set authority. +let hasSideEffects = 1 in + def BSA : UnaryRRE<"bsa", 0xB25A, null_frag, GR64, GR64>; + +// Test access. +let Defs = [CC] in + def TAR : SideEffectBinaryRRE<"tar", 0xB24C, AR32, GR32>; + +//===----------------------------------------------------------------------===// +// Linkage-Stack Instructions. +//===----------------------------------------------------------------------===// + +// Branch and stack. +let hasSideEffects = 1 in + def BAKR : SideEffectBinaryRRE<"bakr", 0xB240, GR64, GR64>; + +// Extract stacked registers. +let hasSideEffects = 1 in { + def EREG : SideEffectBinaryRRE<"ereg", 0xB249, GR32, GR32>; + def EREGG : SideEffectBinaryRRE<"eregg", 0xB90E, GR64, GR64>; +} + +// Extract stacked state. +let hasSideEffects = 1, Defs = [CC] in + def ESTA : UnaryRRE<"esta", 0xB24A, null_frag, GR128, GR32>; + +// Modify stacked state. +let hasSideEffects = 1 in + def MSTA : SideEffectUnaryRRE<"msta", 0xB247, GR128, null_frag>; + +//===----------------------------------------------------------------------===// +// Time-Related Instructions. +//===----------------------------------------------------------------------===// + +// Perform timing facility function. +let hasSideEffects = 1, mayLoad = 1, Uses = [R0L, R1D], Defs = [CC] in + def PTFF : SideEffectInherentE<"ptff", 0x0104>; + +// Set clock. +let hasSideEffects = 1, Defs = [CC] in + def SCK : SideEffectUnaryS<"sck", 0xB204, null_frag, 8>; + +// Set clock programmable field. +let hasSideEffects = 1, Uses = [R0L] in + def SCKPF : SideEffectInherentE<"sckpf", 0x0107>; + +// Set clock comparator. +let hasSideEffects = 1 in + def SCKC : SideEffectUnaryS<"sckc", 0xB206, null_frag, 8>; + +// Set CPU timer. +let hasSideEffects = 1 in + def SPT : SideEffectUnaryS<"spt", 0xB208, null_frag, 8>; + +// Store clock (fast / extended). +let hasSideEffects = 1, Defs = [CC] in { + def STCK : StoreInherentS<"stck", 0xB205, null_frag, 8>; + def STCKF : StoreInherentS<"stckf", 0xB27C, null_frag, 8>; + def STCKE : StoreInherentS<"stcke", 0xB278, null_frag, 16>; +} + +// Store clock comparator. +let hasSideEffects = 1 in + def STCKC : StoreInherentS<"stckc", 0xB207, null_frag, 8>; + +// Store CPU timer. +let hasSideEffects = 1 in + def STPT : StoreInherentS<"stpt", 0xB209, null_frag, 8>; + +//===----------------------------------------------------------------------===// +// CPU-Related Instructions. +//===----------------------------------------------------------------------===// + +// Store CPU address. +let hasSideEffects = 1 in + def STAP : StoreInherentS<"stap", 0xB212, null_frag, 2>; + +// Store CPU ID. +let hasSideEffects = 1 in + def STIDP : StoreInherentS<"stidp", 0xB202, null_frag, 8>; + +// Store system information. +let hasSideEffects = 1, Uses = [R0L, R1L], Defs = [R0L, CC] in + def STSI : StoreInherentS<"stsi", 0xB27D, null_frag, 0>; + +// Store facility list. +let hasSideEffects = 1 in + def STFL : StoreInherentS<"stfl", 0xB2B1, null_frag, 4>; + +// Store facility list extended. +let hasSideEffects = 1, Uses = [R0D], Defs = [R0D, CC] in + def STFLE : StoreInherentS<"stfle", 0xB2B0, null_frag, 0>; + +// Extract CPU attribute. +let hasSideEffects = 1 in + def ECAG : BinaryRSY<"ecag", 0xEB4C, null_frag, GR64>; + +// Extract CPU time. +let hasSideEffects = 1, mayLoad = 1, Defs = [R0D, R1D] in + def ECTG : SideEffectTernarySSF<"ectg", 0xC81, GR64>; + +// Perform topology function. +let hasSideEffects = 1 in + def PTF : UnaryTiedRRE<"ptf", 0xB9A2, GR64>; + +// Perform cryptographic key management operation. +let Predicates = [FeatureMessageSecurityAssist3], + hasSideEffects = 1, Uses = [R0L, R1D] in + def PCKMO : SideEffectInherentRRE<"pckmo", 0xB928>; + +//===----------------------------------------------------------------------===// +// Miscellaneous Instructions. +//===----------------------------------------------------------------------===// + +// Supervisor call. +let hasSideEffects = 1, isCall = 1, Defs = [CC] in + def SVC : SideEffectUnaryI<"svc", 0x0A, imm32zx8>; + +// Monitor call. +let hasSideEffects = 1, isCall = 1 in + def MC : SideEffectBinarySI<"mc", 0xAF, imm32zx8>; + +// Diagnose. +let hasSideEffects = 1, isCall = 1 in + def DIAG : SideEffectTernaryRS<"diag", 0x83, GR32, GR32>; + +// Trace. +let hasSideEffects = 1, mayLoad = 1 in { + def TRACE : SideEffectTernaryRS<"trace", 0x99, GR32, GR32>; + def TRACG : SideEffectTernaryRSY<"tracg", 0xEB0F, GR64, GR64>; +} + +// Trap. +let hasSideEffects = 1 in { + def TRAP2 : SideEffectInherentE<"trap2", 0x01FF>; + def TRAP4 : SideEffectAddressS<"trap4", 0xB2FF, null_frag>; +} + +// Signal processor. +let hasSideEffects = 1, Defs = [CC] in + def SIGP : SideEffectTernaryRS<"sigp", 0xAE, GR64, GR64>; + +// Signal adapter. +let hasSideEffects = 1, Uses = [R0D, R1D, R2D, R3D], Defs = [CC] in + def SIGA : SideEffectAddressS<"siga", 0xB274, null_frag>; + +// Start interpretive execution. +let hasSideEffects = 1, Defs = [CC] in + def SIE : SideEffectUnaryS<"sie", 0xB214, null_frag, 0>; + +//===----------------------------------------------------------------------===// +// CPU-Measurement Facility Instructions (SA23-2260). +//===----------------------------------------------------------------------===// + +// Load program parameter +let hasSideEffects = 1 in + def LPP : SideEffectUnaryS<"lpp", 0xB280, null_frag, 8>; + +// Extract coprocessor-group address. +let hasSideEffects = 1, Defs = [CC] in + def ECPGA : UnaryRRE<"ecpga", 0xB2ED, null_frag, GR32, GR64>; + +// Extract CPU counter. +let hasSideEffects = 1, Defs = [CC] in + def ECCTR : UnaryRRE<"ecctr", 0xB2E4, null_frag, GR64, GR64>; + +// Extract peripheral counter. +let hasSideEffects = 1, Defs = [CC] in + def EPCTR : UnaryRRE<"epctr", 0xB2E5, null_frag, GR64, GR64>; + +// Load CPU-counter-set controls. +let hasSideEffects = 1, Defs = [CC] in + def LCCTL : SideEffectUnaryS<"lcctl", 0xB284, null_frag, 8>; + +// Load peripheral-counter-set controls. +let hasSideEffects = 1, Defs = [CC] in + def LPCTL : SideEffectUnaryS<"lpctl", 0xB285, null_frag, 8>; + +// Load sampling controls. +let hasSideEffects = 1, Defs = [CC] in + def LSCTL : SideEffectUnaryS<"lsctl", 0xB287, null_frag, 0>; + +// Query sampling information. +let hasSideEffects = 1 in + def QSI : StoreInherentS<"qsi", 0xB286, null_frag, 0>; + +// Query counter information. +let hasSideEffects = 1 in + def QCTRI : StoreInherentS<"qctri", 0xB28E, null_frag, 0>; + +// Set CPU counter. +let hasSideEffects = 1, Defs = [CC] in + def SCCTR : SideEffectBinaryRRE<"scctr", 0xB2E0, GR64, GR64>; + +// Set peripheral counter. +let hasSideEffects = 1, Defs = [CC] in + def SPCTR : SideEffectBinaryRRE<"spctr", 0xB2E1, GR64, GR64>; + +//===----------------------------------------------------------------------===// +// I/O Instructions (Principles of Operation, Chapter 14). +//===----------------------------------------------------------------------===// + +// Clear subchannel. +let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in + def CSCH : SideEffectInherentS<"csch", 0xB230, null_frag>; + +// Halt subchannel. +let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in + def HSCH : SideEffectInherentS<"hsch", 0xB231, null_frag>; + +// Modify subchannel. +let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in + def MSCH : SideEffectUnaryS<"msch", 0xB232, null_frag, 0>; + +// Resume subchannel. +let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in + def RSCH : SideEffectInherentS<"rsch", 0xB238, null_frag>; + +// Start subchannel. +let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in + def SSCH : SideEffectUnaryS<"ssch", 0xB233, null_frag, 0>; + +// Store subchannel. +let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in + def STSCH : StoreInherentS<"stsch", 0xB234, null_frag, 0>; + +// Test subchannel. +let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in + def TSCH : StoreInherentS<"tsch", 0xB235, null_frag, 0>; + +// Cancel subchannel. +let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in + def XSCH : SideEffectInherentS<"xsch", 0xB276, null_frag>; + +// Reset channel path. +let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in + def RCHP : SideEffectInherentS<"rchp", 0xB23B, null_frag>; + +// Set channel monitor. +let hasSideEffects = 1, mayLoad = 1, Uses = [R1L, R2D] in + def SCHM : SideEffectInherentS<"schm", 0xB23C, null_frag>; + +// Store channel path status. +let hasSideEffects = 1 in + def STCPS : StoreInherentS<"stcps", 0xB23A, null_frag, 0>; + +// Store channel report word. +let hasSideEffects = 1, Defs = [CC] in + def STCRW : StoreInherentS<"stcrw", 0xB239, null_frag, 0>; + +// Test pending interruption. +let hasSideEffects = 1, Defs = [CC] in + def TPI : StoreInherentS<"tpi", 0xB236, null_frag, 0>; + +// Set address limit. +let hasSideEffects = 1, Uses = [R1L] in + def SAL : SideEffectInherentS<"sal", 0xB237, null_frag>; + diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td index 47d2f75cc11..36809ea81dc 100644 --- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -304,3 +304,13 @@ foreach I = 0-15 in { defm AR32 : SystemZRegClass<"AR32", [i32], 32, (add (sequence "A%u", 0, 15)), 0>; +// Control registers. +class CREG64<bits<16> num, string n> : SystemZReg<n> { + let HWEncoding = num; +} +foreach I = 0-15 in { + def C#I : CREG64<I, "c"#I>, DwarfRegNum<[!add(I, 32)]>; +} +defm CR64 : SystemZRegClass<"CR64", [i64], 64, + (add (sequence "C%u", 0, 15)), 0>; + diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index 2d7d65bddd1..adc9f2976f8 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -708,38 +708,9 @@ def : InstRW<[LSU, Lat30, GroupAlone], (instregex "UPT$")>; def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CKSM$")>; def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CMPSC$")>; -// Move with key -def : InstRW<[FXa, FXa, FXb, LSU, Lat8, GroupAlone], (instregex "MVCK$")>; - -// Monitor call -def : InstRW<[FXb], (instregex "MC$")>; - -// Extract CPU attribute -def : InstRW<[FXb, Lat30], (instregex "ECAG$")>; - -// Extract CPU Time -def : InstRW<[FXa, Lat5, LSU], (instregex "ECTG$")>; - -// Extract PSW -def : InstRW<[FXb, Lat30], (instregex "EPSW$")>; - // Execute def : InstRW<[FXb, GroupAlone], (instregex "EX(RL)?$")>; -// Program return -def : InstRW<[FXb, Lat30], (instregex "PR$")>; - -// Inline assembly -def : InstRW<[LSU, LSU, LSU, FXa, FXa, FXb, Lat9, GroupAlone], - (instregex "STCK(F)?$")>; -def : InstRW<[LSU, LSU, LSU, LSU, FXa, FXa, FXb, FXb, Lat11, GroupAlone], - (instregex "STCKE$")>; -def : InstRW<[FXa, LSU, Lat5], (instregex "STFLE$")>; -def : InstRW<[FXb, Lat30], (instregex "SVC$")>; - -// Store real address -def : InstRW<[FXb, LSU, Lat5], (instregex "STRAG$")>; - //===----------------------------------------------------------------------===// // .insn directive instructions //===----------------------------------------------------------------------===// @@ -1371,5 +1342,162 @@ def : InstRW<[VecStr, Lat5], (instregex "VSTRC(B|F|H)S$")>; def : InstRW<[VecStr], (instregex "VSTRCZ(B|F|H)$")>; def : InstRW<[VecStr, Lat5], (instregex "VSTRCZ(B|F|H)S$")>; + +// -------------------------------- System ---------------------------------- // + +//===----------------------------------------------------------------------===// +// System: Program-Status Word Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "EPSW$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "LPSW(E)?$")>; +def : InstRW<[FXa, Lat3], (instregex "IPK$")>; +def : InstRW<[LSU], (instregex "SPKA$")>; +def : InstRW<[LSU], (instregex "SSM$")>; +def : InstRW<[FXb], (instregex "ST(N|O)SM$")>; +def : InstRW<[FXa, Lat3], (instregex "IAC$")>; +def : InstRW<[LSU], (instregex "SAC(F)?$")>; + +//===----------------------------------------------------------------------===// +// System: Control Register Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat30], (instregex "LCTL(G)?$")>; +def : InstRW<[LSU, Lat30], (instregex "STCT(L|G)$")>; +def : InstRW<[LSU], (instregex "E(P|S)A(I)?R$")>; +def : InstRW<[FXb, Lat30], (instregex "SSA(I)?R$")>; +def : InstRW<[FXb, Lat30], (instregex "ESEA$")>; + +//===----------------------------------------------------------------------===// +// System: Prefix-Register Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat30], (instregex "SPX$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STPX$")>; + +//===----------------------------------------------------------------------===// +// System: Storage-Key and Real Memory Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "ISKE$")>; +def : InstRW<[FXb, Lat30], (instregex "IVSK$")>; +def : InstRW<[FXb, Lat30], (instregex "SSKE(Opt)?$")>; +def : InstRW<[FXb, Lat30], (instregex "RRB(E|M)$")>; +def : InstRW<[FXb, Lat30], (instregex "PFMF$")>; +def : InstRW<[FXb, Lat30], (instregex "TB$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "PGIN$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "PGOUT$")>; + +//===----------------------------------------------------------------------===// +// System: Dynamic-Address-Translation Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat30], (instregex "IPTE(Opt)?(Opt)?$")>; +def : InstRW<[FXb, Lat30], (instregex "IDTE(Opt)?$")>; +def : InstRW<[FXb, Lat30], (instregex "CRDTE(Opt)?$")>; +def : InstRW<[FXb, Lat30], (instregex "PTLB$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "CSP(G)?$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "LPTEA$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "LRA(Y|G)?$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STRAG$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "LURA(G)?$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STUR(A|G)$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "TPROT$")>; + +//===----------------------------------------------------------------------===// +// System: Memory-move Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, FXa, FXb, LSU, Lat8, GroupAlone], (instregex "MVC(K|P|S)$")>; +def : InstRW<[FXa, LSU, Lat6, GroupAlone], (instregex "MVC(S|D)K$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "MVCOS$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "MVPG$")>; + +//===----------------------------------------------------------------------===// +// System: Address-Space Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat30], (instregex "LASP$")>; +def : InstRW<[LSU], (instregex "PALB$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "PC$")>; +def : InstRW<[FXb, Lat30], (instregex "PR$")>; +def : InstRW<[FXb, Lat30], (instregex "PT(I)?$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "RP$")>; +def : InstRW<[FXb, Lat30], (instregex "BS(G|A)$")>; +def : InstRW<[FXb, Lat20], (instregex "TAR$")>; + +//===----------------------------------------------------------------------===// +// System: Linkage-Stack Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "BAKR$")>; +def : InstRW<[FXb, Lat30], (instregex "EREG(G)?$")>; +def : InstRW<[FXb, Lat30], (instregex "(E|M)STA$")>; + +//===----------------------------------------------------------------------===// +// System: Time-Related Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "PTFF$")>; +def : InstRW<[FXb, LSU, Lat20], (instregex "SCK$")>; +def : InstRW<[FXb, Lat30], (instregex "SCKPF$")>; +def : InstRW<[FXb, LSU, Lat20], (instregex "SCKC$")>; +def : InstRW<[LSU, GroupAlone], (instregex "SPT$")>; +def : InstRW<[LSU, LSU, LSU, FXa, FXa, FXb, Lat9, GroupAlone], + (instregex "STCK(F)?$")>; +def : InstRW<[LSU, LSU, LSU, LSU, FXa, FXa, FXb, FXb, Lat11, GroupAlone], + (instregex "STCKE$")>; +def : InstRW<[FXb, LSU, Lat9], (instregex "STCKC$")>; +def : InstRW<[LSU, LSU, FXb, Lat3], (instregex "STPT$")>; + +//===----------------------------------------------------------------------===// +// System: CPU-Related Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat30], (instregex "STAP$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STIDP$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STSI$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STFL(E)?$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "ECAG$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "ECTG$")>; +def : InstRW<[FXb, Lat30], (instregex "PTF$")>; +def : InstRW<[FXb, Lat30], (instregex "PCKMO$")>; + +//===----------------------------------------------------------------------===// +// System: Miscellaneous Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "SVC$")>; +def : InstRW<[FXb], (instregex "MC$")>; +def : InstRW<[FXb, Lat30], (instregex "DIAG$")>; +def : InstRW<[FXb], (instregex "TRAC(E|G)$")>; +def : InstRW<[FXb, Lat30], (instregex "TRAP(2|4)$")>; +def : InstRW<[FXb, Lat30], (instregex "SIGP$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "SIGA$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "SIE$")>; + +//===----------------------------------------------------------------------===// +// System: CPU-Measurement Facility Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb], (instregex "LPP$")>; +def : InstRW<[FXb, Lat30], (instregex "ECPGA$")>; +def : InstRW<[FXb, Lat30], (instregex "E(C|P)CTR$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "L(C|P|S)CTL$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "Q(S|CTR)I$")>; +def : InstRW<[FXb, Lat30], (instregex "S(C|P)CTR$")>; + +//===----------------------------------------------------------------------===// +// System: I/O Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "(C|H|R|X)SCH$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "(M|S|ST|T)SCH$")>; +def : InstRW<[FXb, Lat30], (instregex "RCHP$")>; +def : InstRW<[FXb, Lat30], (instregex "SCHM$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STC(PS|RW)$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "TPI$")>; +def : InstRW<[FXb, Lat30], (instregex "SAL$")>; + } diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index 87403fc4b78..128049a0908 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -641,37 +641,9 @@ def : InstRW<[LSU, Lat30, GroupAlone], (instregex "UPT$")>; def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CKSM$")>; def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CMPSC$")>; -// Move with key -def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>; - -// Monitor call -def : InstRW<[FXU], (instregex "MC$")>; - -// Extract CPU attribute -def : InstRW<[FXU, Lat30], (instregex "ECAG$")>; - -// Extract CPU Time -def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>; - -// Extract PSW -def : InstRW<[FXU, Lat30], (instregex "EPSW$")>; - // Execute def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>; -// Program return -def : InstRW<[FXU, Lat30], (instregex "PR$")>; - -// Inline assembly -def : InstRW<[FXU, LSU, Lat15], (instregex "STCK$")>; -def : InstRW<[FXU, LSU, Lat12], (instregex "STCKF$")>; -def : InstRW<[LSU, FXU, Lat5], (instregex "STCKE$")>; -def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>; -def : InstRW<[FXU, Lat30], (instregex "SVC$")>; - -// Store real address -def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>; - //===----------------------------------------------------------------------===// // .insn directive instructions //===----------------------------------------------------------------------===// @@ -1065,5 +1037,160 @@ def : InstRW<[DFU, Lat9], (instregex "CEXTR$")>; def : InstRW<[LSU, DFU, Lat15], (instregex "TD(C|G)(E|D)T$")>; def : InstRW<[LSU, DFU2, DFU2, Lat15, GroupAlone], (instregex "TD(C|G)XT$")>; + +// -------------------------------- System ---------------------------------- // + +//===----------------------------------------------------------------------===// +// System: Program-Status Word Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, Lat30], (instregex "EPSW$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "LPSW(E)?$")>; +def : InstRW<[FXU, Lat3], (instregex "IPK$")>; +def : InstRW<[LSU], (instregex "SPKA$")>; +def : InstRW<[LSU], (instregex "SSM$")>; +def : InstRW<[FXU], (instregex "ST(N|O)SM$")>; +def : InstRW<[FXU, Lat3], (instregex "IAC$")>; +def : InstRW<[LSU], (instregex "SAC(F)?$")>; + +//===----------------------------------------------------------------------===// +// System: Control Register Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "LCTL(G)?$")>; +def : InstRW<[LSU, Lat30], (instregex "STCT(L|G)$")>; +def : InstRW<[LSU], (instregex "E(P|S)A(I)?R$")>; +def : InstRW<[FXU, Lat30], (instregex "SSA(I)?R$")>; +def : InstRW<[FXU, Lat30], (instregex "ESEA$")>; + +//===----------------------------------------------------------------------===// +// System: Prefix-Register Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "SPX$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STPX$")>; + +//===----------------------------------------------------------------------===// +// System: Storage-Key and Real Memory Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, Lat30], (instregex "ISKE$")>; +def : InstRW<[FXU, Lat30], (instregex "IVSK$")>; +def : InstRW<[FXU, Lat30], (instregex "SSKE(Opt)?$")>; +def : InstRW<[FXU, Lat30], (instregex "RRB(E|M)$")>; +def : InstRW<[FXU, Lat30], (instregex "PFMF$")>; +def : InstRW<[FXU, Lat30], (instregex "TB$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "PGIN$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "PGOUT$")>; + +//===----------------------------------------------------------------------===// +// System: Dynamic-Address-Translation Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "IPTE(Opt)?(Opt)?$")>; +def : InstRW<[FXU, Lat30], (instregex "IDTE(Opt)?$")>; +def : InstRW<[FXU, Lat30], (instregex "PTLB$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "CSP(G)?$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "LPTEA$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "LRA(Y|G)?$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STRAG$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "LURA(G)?$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STUR(A|G)$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "TPROT$")>; + +//===----------------------------------------------------------------------===// +// System: Memory-move Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVC(K|P|S)$")>; +def : InstRW<[LSU, Lat6, GroupAlone], (instregex "MVC(S|D)K$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "MVCOS$")>; +def : InstRW<[LSU, Lat30], (instregex "MVPG$")>; + +//===----------------------------------------------------------------------===// +// System: Address-Space Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "LASP$")>; +def : InstRW<[LSU], (instregex "PALB$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "PC$")>; +def : InstRW<[FXU, Lat30], (instregex "PR$")>; +def : InstRW<[FXU, Lat30], (instregex "PT(I)?$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "RP$")>; +def : InstRW<[FXU, Lat30], (instregex "BS(G|A)$")>; +def : InstRW<[FXU, Lat20], (instregex "TAR$")>; + +//===----------------------------------------------------------------------===// +// System: Linkage-Stack Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "BAKR$")>; +def : InstRW<[FXU, Lat30], (instregex "EREG(G)?$")>; +def : InstRW<[FXU, Lat30], (instregex "(E|M)STA$")>; + +//===----------------------------------------------------------------------===// +// System: Time-Related Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, Lat30], (instregex "PTFF$")>; +def : InstRW<[FXU, LSU, Lat20], (instregex "SCK$")>; +def : InstRW<[FXU, Lat30], (instregex "SCKPF$")>; +def : InstRW<[FXU, LSU, Lat20], (instregex "SCKC$")>; +def : InstRW<[FXU, LSU, Lat20], (instregex "SPT$")>; +def : InstRW<[FXU, LSU, Lat15], (instregex "STCK$")>; +def : InstRW<[FXU, LSU, Lat12], (instregex "STCKF$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STCKE$")>; +def : InstRW<[FXU, LSU, Lat9], (instregex "STCKC$")>; +def : InstRW<[FXU, LSU, Lat8], (instregex "STPT$")>; + +//===----------------------------------------------------------------------===// +// System: CPU-Related Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "STAP$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STIDP$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STSI$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STFL(E)?$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "ECAG$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "ECTG$")>; +def : InstRW<[FXU, Lat30], (instregex "PTF$")>; +def : InstRW<[FXU, Lat30], (instregex "PCKMO$")>; + +//===----------------------------------------------------------------------===// +// System: Miscellaneous Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, Lat30], (instregex "SVC$")>; +def : InstRW<[FXU], (instregex "MC$")>; +def : InstRW<[FXU, Lat30], (instregex "DIAG$")>; +def : InstRW<[FXU], (instregex "TRAC(E|G)$")>; +def : InstRW<[FXU, Lat30], (instregex "TRAP(2|4)$")>; +def : InstRW<[FXU, Lat30], (instregex "SIGP$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "SIGA$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "SIE$")>; + +//===----------------------------------------------------------------------===// +// System: CPU-Measurement Facility Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU], (instregex "LPP$")>; +def : InstRW<[FXU, Lat30], (instregex "ECPGA$")>; +def : InstRW<[FXU, Lat30], (instregex "E(C|P)CTR$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "L(C|P|S)CTL$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "Q(S|CTR)I$")>; +def : InstRW<[FXU, Lat30], (instregex "S(C|P)CTR$")>; + +//===----------------------------------------------------------------------===// +// System: I/O Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, Lat30], (instregex "(C|H|R|X)SCH$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "(M|S|ST|T)SCH$")>; +def : InstRW<[FXU, Lat30], (instregex "RCHP$")>; +def : InstRW<[FXU, Lat30], (instregex "SCHM$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STC(PS|RW)$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "TPI$")>; +def : InstRW<[FXU, Lat30], (instregex "SAL$")>; + } diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index edb5907db2e..76b37845463 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -679,37 +679,9 @@ def : InstRW<[LSU, Lat30, GroupAlone], (instregex "UPT$")>; def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CKSM$")>; def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CMPSC$")>; -// Move with key -def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>; - -// Monitor call -def : InstRW<[FXU], (instregex "MC$")>; - -// Extract CPU attribute -def : InstRW<[FXU, Lat30], (instregex "ECAG$")>; - -// Extract CPU Time -def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>; - -// Extract PSW -def : InstRW<[FXU, Lat30], (instregex "EPSW$")>; - // Execute def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>; -// Program return -def : InstRW<[FXU, Lat30], (instregex "PR$")>; - -// Inline assembly -def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "STCK(F)?$")>; -def : InstRW<[LSU, LSU, LSU, LSU, FXU, FXU, Lat20, GroupAlone], - (instregex "STCKE$")>; -def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>; -def : InstRW<[FXU, Lat30], (instregex "SVC$")>; - -// Store real address -def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>; - //===----------------------------------------------------------------------===// // .insn directive instructions //===----------------------------------------------------------------------===// @@ -1109,5 +1081,161 @@ def : InstRW<[DFU, Lat9], (instregex "CEXTR$")>; def : InstRW<[LSU, DFU, Lat15], (instregex "TD(C|G)(E|D)T$")>; def : InstRW<[LSU, DFU2, DFU2, Lat15, GroupAlone], (instregex "TD(C|G)XT$")>; + +// -------------------------------- System ---------------------------------- // + +//===----------------------------------------------------------------------===// +// System: Program-Status Word Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, Lat30], (instregex "EPSW$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "LPSW(E)?$")>; +def : InstRW<[FXU, Lat3], (instregex "IPK$")>; +def : InstRW<[LSU], (instregex "SPKA$")>; +def : InstRW<[LSU], (instregex "SSM$")>; +def : InstRW<[FXU], (instregex "ST(N|O)SM$")>; +def : InstRW<[FXU, Lat3], (instregex "IAC$")>; +def : InstRW<[LSU], (instregex "SAC(F)?$")>; + +//===----------------------------------------------------------------------===// +// System: Control Register Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "LCTL(G)?$")>; +def : InstRW<[LSU, Lat30], (instregex "STCT(L|G)$")>; +def : InstRW<[LSU], (instregex "E(P|S)A(I)?R$")>; +def : InstRW<[FXU, Lat30], (instregex "SSA(I)?R$")>; +def : InstRW<[FXU, Lat30], (instregex "ESEA$")>; + +//===----------------------------------------------------------------------===// +// System: Prefix-Register Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "SPX$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STPX$")>; + +//===----------------------------------------------------------------------===// +// System: Storage-Key and Real Memory Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, Lat30], (instregex "ISKE$")>; +def : InstRW<[FXU, Lat30], (instregex "IVSK$")>; +def : InstRW<[FXU, Lat30], (instregex "SSKE(Opt)?$")>; +def : InstRW<[FXU, Lat30], (instregex "RRB(E|M)$")>; +def : InstRW<[FXU, Lat30], (instregex "PFMF$")>; +def : InstRW<[FXU, Lat30], (instregex "TB$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "PGIN$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "PGOUT$")>; + +//===----------------------------------------------------------------------===// +// System: Dynamic-Address-Translation Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "IPTE(Opt)?(Opt)?$")>; +def : InstRW<[FXU, Lat30], (instregex "IDTE(Opt)?$")>; +def : InstRW<[FXU, Lat30], (instregex "CRDTE(Opt)?$")>; +def : InstRW<[FXU, Lat30], (instregex "PTLB$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "CSP(G)?$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "LPTEA$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "LRA(Y|G)?$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STRAG$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "LURA(G)?$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STUR(A|G)$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "TPROT$")>; + +//===----------------------------------------------------------------------===// +// System: Memory-move Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVC(K|P|S)$")>; +def : InstRW<[LSU, Lat6, GroupAlone], (instregex "MVC(S|D)K$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "MVCOS$")>; +def : InstRW<[LSU, Lat30], (instregex "MVPG$")>; + +//===----------------------------------------------------------------------===// +// System: Address-Space Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "LASP$")>; +def : InstRW<[LSU], (instregex "PALB$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "PC$")>; +def : InstRW<[FXU, Lat30], (instregex "PR$")>; +def : InstRW<[FXU, Lat30], (instregex "PT(I)?$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "RP$")>; +def : InstRW<[FXU, Lat30], (instregex "BS(G|A)$")>; +def : InstRW<[FXU, Lat20], (instregex "TAR$")>; + +//===----------------------------------------------------------------------===// +// System: Linkage-Stack Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "BAKR$")>; +def : InstRW<[FXU, Lat30], (instregex "EREG(G)?$")>; +def : InstRW<[FXU, Lat30], (instregex "(E|M)STA$")>; + +//===----------------------------------------------------------------------===// +// System: Time-Related Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, Lat30], (instregex "PTFF$")>; +def : InstRW<[FXU, LSU, Lat20], (instregex "SCK$")>; +def : InstRW<[FXU, Lat30], (instregex "SCKPF$")>; +def : InstRW<[FXU, LSU, Lat20], (instregex "SCKC$")>; +def : InstRW<[FXU, LSU, Lat20], (instregex "SPT$")>; +def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "STCK(F)?$")>; +def : InstRW<[LSU, LSU, LSU, LSU, FXU, FXU, Lat20, GroupAlone], + (instregex "STCKE$")>; +def : InstRW<[FXU, LSU, Lat9], (instregex "STCKC$")>; +def : InstRW<[FXU, LSU, Lat8], (instregex "STPT$")>; + +//===----------------------------------------------------------------------===// +// System: CPU-Related Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, LSU, Lat30], (instregex "STAP$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STIDP$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STSI$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STFL(E)?$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "ECAG$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "ECTG$")>; +def : InstRW<[FXU, Lat30], (instregex "PTF$")>; +def : InstRW<[FXU, Lat30], (instregex "PCKMO$")>; + +//===----------------------------------------------------------------------===// +// System: Miscellaneous Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, Lat30], (instregex "SVC$")>; +def : InstRW<[FXU], (instregex "MC$")>; +def : InstRW<[FXU, Lat30], (instregex "DIAG$")>; +def : InstRW<[FXU], (instregex "TRAC(E|G)$")>; +def : InstRW<[FXU, Lat30], (instregex "TRAP(2|4)$")>; +def : InstRW<[FXU, Lat30], (instregex "SIGP$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "SIGA$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "SIE$")>; + +//===----------------------------------------------------------------------===// +// System: CPU-Measurement Facility Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU], (instregex "LPP$")>; +def : InstRW<[FXU, Lat30], (instregex "ECPGA$")>; +def : InstRW<[FXU, Lat30], (instregex "E(C|P)CTR$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "L(C|P|S)CTL$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "Q(S|CTR)I$")>; +def : InstRW<[FXU, Lat30], (instregex "S(C|P)CTR$")>; + +//===----------------------------------------------------------------------===// +// System: I/O Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXU, Lat30], (instregex "(C|H|R|X)SCH$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "(M|S|ST|T)SCH$")>; +def : InstRW<[FXU, Lat30], (instregex "RCHP$")>; +def : InstRW<[FXU, Lat30], (instregex "SCHM$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "STC(PS|RW)$")>; +def : InstRW<[FXU, LSU, Lat30], (instregex "TPI$")>; +def : InstRW<[FXU, Lat30], (instregex "SAL$")>; + } diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp index 0ab0c2f2591..eb4a0962f7e 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -37,12 +37,13 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU, const TargetMachine &TM) : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false), HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false), - HasPopulationCount(false), HasMessageSecurityAssist4(false), + HasPopulationCount(false), HasMessageSecurityAssist3(false), + HasMessageSecurityAssist4(false), HasResetReferenceBitsMultiple(false), HasFastSerialization(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), HasExecutionHint(false), HasLoadAndTrap(false), HasTransactionalExecution(false), HasProcessorAssist(false), - HasDFPZonedConversion(false), + HasDFPZonedConversion(false), HasEnhancedDAT2(false), HasVector(false), HasLoadStoreOnCond2(false), HasLoadAndZeroRightmostByte(false), HasMessageSecurityAssist5(false), HasDFPPackedConversion(false), diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.h b/llvm/lib/Target/SystemZ/SystemZSubtarget.h index be480f03c57..b05a1bb6caf 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.h +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.h @@ -39,7 +39,9 @@ protected: bool HasHighWord; bool HasFPExtension; bool HasPopulationCount; + bool HasMessageSecurityAssist3; bool HasMessageSecurityAssist4; + bool HasResetReferenceBitsMultiple; bool HasFastSerialization; bool HasInterlockedAccess1; bool HasMiscellaneousExtensions; @@ -48,6 +50,7 @@ protected: bool HasTransactionalExecution; bool HasProcessorAssist; bool HasDFPZonedConversion; + bool HasEnhancedDAT2; bool HasVector; bool HasLoadStoreOnCond2; bool HasLoadAndZeroRightmostByte; @@ -109,9 +112,18 @@ public: bool hasPopulationCount() const { return HasPopulationCount; } // Return true if the target has the message-security-assist + // extension facility 3. + bool hasMessageSecurityAssist3() const { return HasMessageSecurityAssist3; } + + // Return true if the target has the message-security-assist // extension facility 4. bool hasMessageSecurityAssist4() const { return HasMessageSecurityAssist4; } + // Return true if the target has the reset-reference-bits-multiple facility. + bool hasResetReferenceBitsMultiple() const { + return HasResetReferenceBitsMultiple; + } + // Return true if the target has the fast-serialization facility. bool hasFastSerialization() const { return HasFastSerialization; } @@ -138,6 +150,9 @@ public: // Return true if the target has the DFP zoned-conversion facility. bool hasDFPZonedConversion() const { return HasDFPZonedConversion; } + // Return true if the target has the enhanced-DAT facility 2. + bool hasEnhancedDAT2() const { return HasEnhancedDAT2; } + // Return true if the target has the load-and-zero-rightmost-byte facility. bool hasLoadAndZeroRightmostByte() const { return HasLoadAndZeroRightmostByte; diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt index 9775466137c..2ca19363c46 100644 --- a/llvm/test/MC/Disassembler/SystemZ/insns.txt +++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt @@ -1222,6 +1222,18 @@ # CHECK: b 4095(%r15,%r1) 0x47 0xff 0x1f 0xff +# CHECK: bakr %r0, %r0 +0xb2 0x40 0x00 0x00 + +# CHECK: bakr %r0, %r15 +0xb2 0x40 0x00 0x0f + +# CHECK: bakr %r15, %r0 +0xb2 0x40 0x00 0xf0 + +# CHECK: bakr %r7, %r8 +0xb2 0x40 0x00 0x78 + # CHECK: bal %r0, 0 0x45 0x00 0x00 0x00 @@ -1483,6 +1495,30 @@ # CHECK: bctr %r15, %r9 0x06 0xf9 +# CHECK: bsa %r0, %r0 +0xb2 0x5a 0x00 0x00 + +# CHECK: bsa %r0, %r15 +0xb2 0x5a 0x00 0x0f + +# CHECK: bsa %r15, %r0 +0xb2 0x5a 0x00 0xf0 + +# CHECK: bsa %r7, %r8 +0xb2 0x5a 0x00 0x78 + +# CHECK: bsg %r0, %r0 +0xb2 0x58 0x00 0x00 + +# CHECK: bsg %r0, %r15 +0xb2 0x58 0x00 0x0f + +# CHECK: bsg %r15, %r0 +0xb2 0x58 0x00 0xf0 + +# CHECK: bsg %r7, %r8 +0xb2 0x58 0x00 0x78 + # CHECK: bsm %r0, %r1 0x0b 0x01 @@ -4726,6 +4762,24 @@ # CHECK: crb %r0, %r0, 15, 0 0xec 0x00 0x00 0x00 0xf0 0xf6 +# CHECK: crdte %r0, %r0, %r0 +0xb9 0x8f 0x00 0x00 + +# CHECK: crdte %r0, %r0, %r14 +0xb9 0x8f 0x00 0x0e + +# CHECK: crdte %r0, %r15, %r0 +0xb9 0x8f 0xf0 0x00 + +# CHECK: crdte %r14, %r0, %r0 +0xb9 0x8f 0x00 0xe0 + +# CHECK: crdte %r0, %r0, %r0, 15 +0xb9 0x8f 0x0f 0x00 + +# CHECK: crdte %r4, %r5, %r6, 7 +0xb9 0x8f 0x57 0x46 + # CHECK: crth %r0, %r1 0xb9 0x72 0x20 0x01 @@ -4768,6 +4822,9 @@ # CHECK: cs %r15, %r0, 0 0xba 0xf0 0x00 0x00 +# CHECK: csch +0xb2 0x30 0x00 0x00 + # CHECK: csdtr %r0, %f0, 0 0xb3 0xe3 0x00 0x00 @@ -4816,6 +4873,30 @@ # CHECK: csg %r15, %r0, 0 0xeb 0xf0 0x00 0x00 0x00 0x30 +# CHECK: csp %r0, %r0 +0xb2 0x50 0x00 0x00 + +# CHECK: csp %r0, %r15 +0xb2 0x50 0x00 0x0f + +# CHECK: csp %r14, %r0 +0xb2 0x50 0x00 0xe0 + +# CHECK: csp %r6, %r8 +0xb2 0x50 0x00 0x68 + +# CHECK: cspg %r0, %r0 +0xb9 0x8a 0x00 0x00 + +# CHECK: cspg %r0, %r15 +0xb9 0x8a 0x00 0x0f + +# CHECK: cspg %r14, %r0 +0xb9 0x8a 0x00 0xe0 + +# CHECK: cspg %r6, %r8 +0xb9 0x8a 0x00 0x68 + # CHECK: csst 0, 0, %r0 0xc8 0x02 0x00 0x00 0x00 0x00 @@ -5767,6 +5848,36 @@ # CHECK: der %f15, %f0 0x3d 0xf0 +# CHECK: diag %r0, %r0, 0 +0x83 0x00 0x00 0x00 + +# CHECK: diag %r0, %r15, 0 +0x83 0x0f 0x00 0x00 + +# CHECK: diag %r14, %r15, 0 +0x83 0xef 0x00 0x00 + +# CHECK: diag %r15, %r15, 0 +0x83 0xff 0x00 0x00 + +# CHECK: diag %r0, %r0, 4095 +0x83 0x00 0x0f 0xff + +# CHECK: diag %r0, %r0, 1 +0x83 0x00 0x00 0x01 + +# CHECK: diag %r0, %r0, 0(%r1) +0x83 0x00 0x10 0x00 + +# CHECK: diag %r0, %r0, 0(%r15) +0x83 0x00 0xf0 0x00 + +# CHECK: diag %r0, %r0, 4095(%r1) +0x83 0x00 0x1f 0xff + +# CHECK: diag %r0, %r0, 4095(%r15) +0x83 0x00 0xff 0xff + # CHECK: didbr %f0, %f0, %f0, 1 0xb3 0x5b 0x01 0x00 @@ -6136,6 +6247,30 @@ # CHECK: ecag %r0, %r0, 524287(%r15) 0xeb 0x00 0xff 0xff 0x7f 0x4c +# CHECK: ecctr %r0, %r0 +0xb2 0xe4 0x00 0x00 + +# CHECK: ecctr %r0, %r15 +0xb2 0xe4 0x00 0x0f + +# CHECK: ecctr %r15, %r0 +0xb2 0xe4 0x00 0xf0 + +# CHECK: ecctr %r7, %r8 +0xb2 0xe4 0x00 0x78 + +# CHECK: ecpga %r0, %r0 +0xb2 0xed 0x00 0x00 + +# CHECK: ecpga %r0, %r15 +0xb2 0xed 0x00 0x0f + +# CHECK: ecpga %r15, %r0 +0xb2 0xed 0x00 0xf0 + +# CHECK: ecpga %r7, %r8 +0xb2 0xed 0x00 0x78 + # CHECK: ectg 0, 0, %r0 0xc8 0x01 0x00 0x00 0x00 0x00 @@ -6262,6 +6397,36 @@ # CHECK: efpc %r15 0xb3 0x8c 0x00 0xf0 +# CHECK: epar %r0 +0xb2 0x26 0x00 0x00 + +# CHECK: epar %r1 +0xb2 0x26 0x00 0x10 + +# CHECK: epar %r15 +0xb2 0x26 0x00 0xf0 + +# CHECK: epair %r0 +0xb9 0x9a 0x00 0x00 + +# CHECK: epair %r1 +0xb9 0x9a 0x00 0x10 + +# CHECK: epair %r15 +0xb9 0x9a 0x00 0xf0 + +# CHECK: epctr %r0, %r0 +0xb2 0xe5 0x00 0x00 + +# CHECK: epctr %r0, %r15 +0xb2 0xe5 0x00 0x0f + +# CHECK: epctr %r15, %r0 +0xb2 0xe5 0x00 0xf0 + +# CHECK: epctr %r7, %r8 +0xb2 0xe5 0x00 0x78 + # CHECK: epsw %r0, %r0 0xb9 0x8d 0x00 0x00 @@ -6274,6 +6439,48 @@ # CHECK: epsw %r6, %r8 0xb9 0x8d 0x00 0x68 +# CHECK: ereg %r0, %r0 +0xb2 0x49 0x00 0x00 + +# CHECK: ereg %r0, %r15 +0xb2 0x49 0x00 0x0f + +# CHECK: ereg %r15, %r0 +0xb2 0x49 0x00 0xf0 + +# CHECK: ereg %r7, %r8 +0xb2 0x49 0x00 0x78 + +# CHECK: eregg %r0, %r0 +0xb9 0x0e 0x00 0x00 + +# CHECK: eregg %r0, %r15 +0xb9 0x0e 0x00 0x0f + +# CHECK: eregg %r15, %r0 +0xb9 0x0e 0x00 0xf0 + +# CHECK: eregg %r7, %r8 +0xb9 0x0e 0x00 0x78 + +# CHECK: esar %r0 +0xb2 0x27 0x00 0x00 + +# CHECK: esar %r1 +0xb2 0x27 0x00 0x10 + +# CHECK: esar %r15 +0xb2 0x27 0x00 0xf0 + +# CHECK: esair %r0 +0xb9 0x9b 0x00 0x00 + +# CHECK: esair %r1 +0xb9 0x9b 0x00 0x10 + +# CHECK: esair %r15 +0xb9 0x9b 0x00 0xf0 + # CHECK: esdtr %f0, %f9 0xb3 0xe7 0x00 0x09 @@ -6286,6 +6493,27 @@ # CHECK: esdtr %f15, %f9 0xb3 0xe7 0x00 0xf9 +# CHECK: esea %r0 +0xb9 0x9d 0x00 0x00 + +# CHECK: esea %r1 +0xb9 0x9d 0x00 0x10 + +# CHECK: esea %r15 +0xb9 0x9d 0x00 0xf0 + +# CHECK: esta %r0, %r0 +0xb2 0x4a 0x00 0x00 + +# CHECK: esta %r0, %r15 +0xb2 0x4a 0x00 0x0f + +# CHECK: esta %r14, %r0 +0xb2 0x4a 0x00 0xe0 + +# CHECK: esta %r6, %r8 +0xb2 0x4a 0x00 0x68 + # CHECK: esxtr %f0, %f8 0xb3 0xef 0x00 0x08 @@ -6535,6 +6763,18 @@ # CHECK: her %f15, %f0 0x34 0xf0 +# CHECK: hsch +0xb2 0x31 0x00 0x00 + +# CHECK: iac %r0 +0xb2 0x24 0x00 0x00 + +# CHECK: iac %r1 +0xb2 0x24 0x00 0x10 + +# CHECK: iac %r15 +0xb2 0x24 0x00 0xf0 + # CHECK: ic %r0, 0 0x43 0x00 0x00 0x00 @@ -6667,6 +6907,24 @@ # CHECK: icy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x73 +# CHECK: idte %r0, %r0, %r0 +0xb9 0x8e 0x00 0x00 + +# CHECK: idte %r0, %r0, %r15 +0xb9 0x8e 0x00 0x0f + +# CHECK: idte %r0, %r15, %r0 +0xb9 0x8e 0xf0 0x00 + +# CHECK: idte %r15, %r0, %r0 +0xb9 0x8e 0x00 0xf0 + +# CHECK: idte %r0, %r0, %r0, 15 +0xb9 0x8e 0x0f 0x00 + +# CHECK: idte %r4, %r5, %r6, 7 +0xb9 0x8e 0x57 0x46 + # CHECK: iedtr %f0, %f0, %f0 0xb3 0xf6 0x00 0x00 @@ -6769,6 +7027,9 @@ # CHECK: iill %r15, 0 0xa5 0xf3 0x00 0x00 +# CHECK: ipk +0xb2 0x0b 0x00 0x00 + # CHECK: ipm %r0 0xb2 0x22 0x00 0x00 @@ -6778,6 +7039,48 @@ # CHECK: ipm %r15 0xb2 0x22 0x00 0xf0 +# CHECK: ipte %r0, %r0 +0xb2 0x21 0x00 0x00 + +# CHECK: ipte %r0, %r15 +0xb2 0x21 0x00 0x0f + +# CHECK: ipte %r15, %r0 +0xb2 0x21 0x00 0xf0 + +# CHECK: ipte %r0, %r0, %r15 +0xb2 0x21 0xf0 0x00 + +# CHECK: ipte %r0, %r0, %r0, 15 +0xb2 0x21 0x0f 0x00 + +# CHECK: ipte %r7, %r8, %r9, 10 +0xb2 0x21 0x9a 0x78 + +# CHECK: iske %r0, %r0 +0xb2 0x29 0x00 0x00 + +# CHECK: iske %r0, %r15 +0xb2 0x29 0x00 0x0f + +# CHECK: iske %r15, %r0 +0xb2 0x29 0x00 0xf0 + +# CHECK: iske %r7, %r8 +0xb2 0x29 0x00 0x78 + +# CHECK: ivsk %r0, %r0 +0xb2 0x23 0x00 0x00 + +# CHECK: ivsk %r0, %r15 +0xb2 0x23 0x00 0x0f + +# CHECK: ivsk %r15, %r0 +0xb2 0x23 0x00 0xf0 + +# CHECK: ivsk %r7, %r8 +0xb2 0x23 0x00 0x78 + # CHECK: kdb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x18 @@ -7402,6 +7705,36 @@ # CHECK: laog %r15, %r0, 0 0xeb 0xf0 0x00 0x00 0x00 0xe6 +# CHECK: lasp 0, 0 +0xe5 0x00 0x00 0x00 0x00 0x00 + +# CHECK: lasp 0(%r1), 0(%r2) +0xe5 0x00 0x10 0x00 0x20 0x00 + +# CHECK: lasp 160(%r1), 320(%r15) +0xe5 0x00 0x10 0xa0 0xf1 0x40 + +# CHECK: lasp 0(%r1), 4095 +0xe5 0x00 0x10 0x00 0x0f 0xff + +# CHECK: lasp 0(%r1), 4095(%r2) +0xe5 0x00 0x10 0x00 0x2f 0xff + +# CHECK: lasp 0(%r1), 4095(%r15) +0xe5 0x00 0x10 0x00 0xff 0xff + +# CHECK: lasp 0(%r1), 0 +0xe5 0x00 0x10 0x00 0x00 0x00 + +# CHECK: lasp 0(%r15), 0 +0xe5 0x00 0xf0 0x00 0x00 0x00 + +# CHECK: lasp 4095(%r1), 0 +0xe5 0x00 0x1f 0xff 0x00 0x00 + +# CHECK: lasp 4095(%r15), 0 +0xe5 0x00 0xff 0xff 0x00 0x00 + # CHECK: lat %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x9f @@ -7597,6 +7930,24 @@ # CHECK: lbr %r15, %r0 0xb9 0x26 0x00 0xf0 +# CHECK: lcctl 0 +0xb2 0x84 0x00 0x00 + +# CHECK: lcctl 0(%r1) +0xb2 0x84 0x10 0x00 + +# CHECK: lcctl 0(%r15) +0xb2 0x84 0xf0 0x00 + +# CHECK: lcctl 4095 +0xb2 0x84 0x0f 0xff + +# CHECK: lcctl 4095(%r1) +0xb2 0x84 0x1f 0xff + +# CHECK: lcctl 4095(%r15) +0xb2 0x84 0xff 0xff + # CHECK: lcdbr %f0, %f9 0xb3 0x13 0x00 0x09 @@ -7680,6 +8031,75 @@ # CHECK: lcr %r7, %r8 0x13 0x78 +# CHECK: lctl %c0, %c0, 0 +0xb7 0x00 0x00 0x00 + +# CHECK: lctl %c0, %c15, 0 +0xb7 0x0f 0x00 0x00 + +# CHECK: lctl %c14, %c15, 0 +0xb7 0xef 0x00 0x00 + +# CHECK: lctl %c15, %c15, 0 +0xb7 0xff 0x00 0x00 + +# CHECK: lctl %c0, %c0, 4095 +0xb7 0x00 0x0f 0xff + +# CHECK: lctl %c0, %c0, 1 +0xb7 0x00 0x00 0x01 + +# CHECK: lctl %c0, %c0, 0(%r1) +0xb7 0x00 0x10 0x00 + +# CHECK: lctl %c0, %c0, 0(%r15) +0xb7 0x00 0xf0 0x00 + +# CHECK: lctl %c0, %c0, 4095(%r1) +0xb7 0x00 0x1f 0xff + +# CHECK: lctl %c0, %c0, 4095(%r15) +0xb7 0x00 0xff 0xff + +# CHECK: lctlg %c0, %c0, 0 +0xeb 0x00 0x00 0x00 0x00 0x2f + +# CHECK: lctlg %c0, %c15, 0 +0xeb 0x0f 0x00 0x00 0x00 0x2f + +# CHECK: lctlg %c14, %c15, 0 +0xeb 0xef 0x00 0x00 0x00 0x2f + +# CHECK: lctlg %c15, %c15, 0 +0xeb 0xff 0x00 0x00 0x00 0x2f + +# CHECK: lctlg %c0, %c0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x2f + +# CHECK: lctlg %c0, %c0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x2f + +# CHECK: lctlg %c0, %c0, 0 +0xeb 0x00 0x00 0x00 0x00 0x2f + +# CHECK: lctlg %c0, %c0, 1 +0xeb 0x00 0x00 0x01 0x00 0x2f + +# CHECK: lctlg %c0, %c0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x2f + +# CHECK: lctlg %c0, %c0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x2f + +# CHECK: lctlg %c0, %c0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x2f + +# CHECK: lctlg %c0, %c0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x2f + +# CHECK: lctlg %c0, %c0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x2f + # CHECK: lcxbr %f0, %f8 0xb3 0x43 0x00 0x08 @@ -9426,6 +9846,24 @@ # CHECK: locgr %r11, %r3, 15 0xb9 0xe2 0xf0 0xb3 +# CHECK: lpctl 0 +0xb2 0x85 0x00 0x00 + +# CHECK: lpctl 0(%r1) +0xb2 0x85 0x10 0x00 + +# CHECK: lpctl 0(%r15) +0xb2 0x85 0xf0 0x00 + +# CHECK: lpctl 4095 +0xb2 0x85 0x0f 0xff + +# CHECK: lpctl 4095(%r1) +0xb2 0x85 0x1f 0xff + +# CHECK: lpctl 4095(%r15) +0xb2 0x85 0xff 0xff + # CHECK: lpd %r0, 0, 0 0xc8 0x04 0x00 0x00 0x00 0x00 @@ -9540,6 +9978,24 @@ # CHECK: lpgr %r7, %r8 0xb9 0x00 0x00 0x78 +# CHECK: lpp 0 +0xb2 0x80 0x00 0x00 + +# CHECK: lpp 0(%r1) +0xb2 0x80 0x10 0x00 + +# CHECK: lpp 0(%r15) +0xb2 0x80 0xf0 0x00 + +# CHECK: lpp 4095 +0xb2 0x80 0x0f 0xff + +# CHECK: lpp 4095(%r1) +0xb2 0x80 0x1f 0xff + +# CHECK: lpp 4095(%r15) +0xb2 0x80 0xff 0xff + # CHECK: lpq %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x8f @@ -9582,6 +10038,60 @@ # CHECK: lpr %r7, %r8 0x10 0x78 +# CHECK: lpsw 0 +0x82 0x00 0x00 0x00 + +# CHECK: lpsw 0(%r1) +0x82 0x00 0x10 0x00 + +# CHECK: lpsw 0(%r15) +0x82 0x00 0xf0 0x00 + +# CHECK: lpsw 4095 +0x82 0x00 0x0f 0xff + +# CHECK: lpsw 4095(%r1) +0x82 0x00 0x1f 0xff + +# CHECK: lpsw 4095(%r15) +0x82 0x00 0xff 0xff + +# CHECK: lpswe 0 +0xb2 0xb2 0x00 0x00 + +# CHECK: lpswe 0(%r1) +0xb2 0xb2 0x10 0x00 + +# CHECK: lpswe 0(%r15) +0xb2 0xb2 0xf0 0x00 + +# CHECK: lpswe 4095 +0xb2 0xb2 0x0f 0xff + +# CHECK: lpswe 4095(%r1) +0xb2 0xb2 0x1f 0xff + +# CHECK: lpswe 4095(%r15) +0xb2 0xb2 0xff 0xff + +# CHECK: lptea %r0, %r0, %r0, 0 +0xb9 0xaa 0x00 0x00 + +# CHECK: lptea %r0, %r0, %r0, 15 +0xb9 0xaa 0x0f 0x00 + +# CHECK: lptea %r0, %r0, %r15, 0 +0xb9 0xaa 0x00 0x0f + +# CHECK: lptea %r0, %r15, %r0, 0 +0xb9 0xaa 0xf0 0x00 + +# CHECK: lptea %r4, %r5, %r6, 7 +0xb9 0xaa 0x57 0x46 + +# CHECK: lptea %r15, %r0, %r0, 0 +0xb9 0xaa 0x00 0xf0 + # CHECK: lpxbr %f0, %f8 0xb3 0x40 0x00 0x08 @@ -9618,6 +10128,87 @@ # CHECK: lr %r15, %r9 0x18 0xf9 +# CHECK: lra %r0, 0 +0xb1 0x00 0x00 0x00 + +# CHECK: lra %r0, 4095 +0xb1 0x00 0x0f 0xff + +# CHECK: lra %r0, 0(%r1) +0xb1 0x00 0x10 0x00 + +# CHECK: lra %r0, 0(%r15) +0xb1 0x00 0xf0 0x00 + +# CHECK: lra %r0, 4095(%r1,%r15) +0xb1 0x01 0xff 0xff + +# CHECK: lra %r0, 4095(%r15,%r1) +0xb1 0x0f 0x1f 0xff + +# CHECK: lra %r15, 0 +0xb1 0xf0 0x00 0x00 + +# CHECK: lrag %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x03 + +# CHECK: lrag %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x03 + +# CHECK: lrag %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x03 + +# CHECK: lrag %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x03 + +# CHECK: lrag %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x03 + +# CHECK: lrag %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x03 + +# CHECK: lrag %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x03 + +# CHECK: lrag %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x03 + +# CHECK: lrag %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x03 + +# CHECK: lrag %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x03 + +# CHECK: lray %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x13 + +# CHECK: lray %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x13 + +# CHECK: lray %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x13 + +# CHECK: lray %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x13 + +# CHECK: lray %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x13 + +# CHECK: lray %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x13 + +# CHECK: lray %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x13 + +# CHECK: lray %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x13 + +# CHECK: lray %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x13 + +# CHECK: lray %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x13 + # CHECK: lrv %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x1e @@ -9738,6 +10329,24 @@ # CHECK: lrvr %r15, %r15 0xb9 0x1f 0x00 0xff +# CHECK: lsctl 0 +0xb2 0x87 0x00 0x00 + +# CHECK: lsctl 0(%r1) +0xb2 0x87 0x10 0x00 + +# CHECK: lsctl 0(%r15) +0xb2 0x87 0xf0 0x00 + +# CHECK: lsctl 4095 +0xb2 0x87 0x0f 0xff + +# CHECK: lsctl 4095(%r1) +0xb2 0x87 0x1f 0xff + +# CHECK: lsctl 4095(%r15) +0xb2 0x87 0xff 0xff + # CHECK: lt %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x12 @@ -9960,6 +10569,30 @@ # CHECK: ltxtr %f13, %f9 0xb3 0xde 0x00 0xd9 +# CHECK: lura %r0, %r0 +0xb2 0x4b 0x00 0x00 + +# CHECK: lura %r0, %r15 +0xb2 0x4b 0x00 0x0f + +# CHECK: lura %r15, %r0 +0xb2 0x4b 0x00 0xf0 + +# CHECK: lura %r7, %r8 +0xb2 0x4b 0x00 0x78 + +# CHECK: lurag %r0, %r0 +0xb9 0x05 0x00 0x00 + +# CHECK: lurag %r0, %r15 +0xb9 0x05 0x00 0x0f + +# CHECK: lurag %r15, %r0 +0xb9 0x05 0x00 0xf0 + +# CHECK: lurag %r7, %r8 +0xb9 0x05 0x00 0x78 + # CHECK: lxd %f0, 4095 0xed 0x00 0x0f 0xff 0x00 0x25 @@ -11031,6 +11664,24 @@ # CHECK: ms %r15, 0 0x71 0xf0 0x00 0x00 +# CHECK: msch 0 +0xb2 0x32 0x00 0x00 + +# CHECK: msch 0(%r1) +0xb2 0x32 0x10 0x00 + +# CHECK: msch 0(%r15) +0xb2 0x32 0xf0 0x00 + +# CHECK: msch 4095 +0xb2 0x32 0x0f 0xff + +# CHECK: msch 4095(%r1) +0xb2 0x32 0x1f 0xff + +# CHECK: msch 4095(%r15) +0xb2 0x32 0xff 0xff + # CHECK: msd %f0, %f0, 0 0xed 0x00 0x00 0x00 0x00 0x3f @@ -11343,6 +11994,15 @@ # CHECK: msr %r7, %r8 0xb2 0x52 0x00 0x78 +# CHECK: msta %r0 +0xb2 0x47 0x00 0x00 + +# CHECK: msta %r2 +0xb2 0x47 0x00 0x20 + +# CHECK: msta %r14 +0xb2 0x47 0x00 0xe0 + # CHECK: msy %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x51 @@ -11409,6 +12069,36 @@ # CHECK: mvc 0(256,%r15), 0 0xd2 0xff 0xf0 0x00 0x00 0x00 +# CHECK: mvcdk 0, 0 +0xe5 0x0f 0x00 0x00 0x00 0x00 + +# CHECK: mvcdk 0(%r1), 0(%r2) +0xe5 0x0f 0x10 0x00 0x20 0x00 + +# CHECK: mvcdk 160(%r1), 320(%r15) +0xe5 0x0f 0x10 0xa0 0xf1 0x40 + +# CHECK: mvcdk 0(%r1), 4095 +0xe5 0x0f 0x10 0x00 0x0f 0xff + +# CHECK: mvcdk 0(%r1), 4095(%r2) +0xe5 0x0f 0x10 0x00 0x2f 0xff + +# CHECK: mvcdk 0(%r1), 4095(%r15) +0xe5 0x0f 0x10 0x00 0xff 0xff + +# CHECK: mvcdk 0(%r1), 0 +0xe5 0x0f 0x10 0x00 0x00 0x00 + +# CHECK: mvcdk 0(%r15), 0 +0xe5 0x0f 0xf0 0x00 0x00 0x00 + +# CHECK: mvcdk 4095(%r1), 0 +0xe5 0x0f 0x1f 0xff 0x00 0x00 + +# CHECK: mvcdk 4095(%r15), 0 +0xe5 0x0f 0xff 0xff 0x00 0x00 + # CHECK: mvcin 0(1), 0 0xe8 0x00 0x00 0x00 0x00 0x00 @@ -11529,6 +12219,132 @@ # CHECK: mvclu %r14, %r0, 0 0xeb 0xe0 0x00 0x00 0x00 0x8e +# CHECK: mvcos 0, 0, %r0 +0xc8 0x00 0x00 0x00 0x00 0x00 + +# CHECK: mvcos 0(%r1), 0(%r15), %r2 +0xc8 0x20 0x10 0x00 0xf0 0x00 + +# CHECK: mvcos 1(%r1), 0(%r15), %r2 +0xc8 0x20 0x10 0x01 0xf0 0x00 + +# CHECK: mvcos 4095(%r1), 0(%r15), %r2 +0xc8 0x20 0x1f 0xff 0xf0 0x00 + +# CHECK: mvcos 0(%r1), 1(%r15), %r2 +0xc8 0x20 0x10 0x00 0xf0 0x01 + +# CHECK: mvcos 0(%r1), 4095(%r15), %r2 +0xc8 0x20 0x10 0x00 0xff 0xff + +# CHECK: mvcp 0(%r0), 0, %r3 +0xda 0x03 0x00 0x00 0x00 0x00 + +# CHECK: mvcp 0(%r1), 0, %r3 +0xda 0x13 0x00 0x00 0x00 0x00 + +# CHECK: mvcp 0(%r1), 0(%r1), %r3 +0xda 0x13 0x00 0x00 0x10 0x00 + +# CHECK: mvcp 0(%r1), 0(%r15), %r3 +0xda 0x13 0x00 0x00 0xf0 0x00 + +# CHECK: mvcp 0(%r1), 4095, %r3 +0xda 0x13 0x00 0x00 0x0f 0xff + +# CHECK: mvcp 0(%r1), 4095(%r1), %r3 +0xda 0x13 0x00 0x00 0x1f 0xff + +# CHECK: mvcp 0(%r1), 4095(%r15), %r3 +0xda 0x13 0x00 0x00 0xff 0xff + +# CHECK: mvcp 0(%r2,%r1), 0, %r3 +0xda 0x23 0x10 0x00 0x00 0x00 + +# CHECK: mvcp 0(%r2,%r15), 0, %r3 +0xda 0x23 0xf0 0x00 0x00 0x00 + +# CHECK: mvcp 4095(%r2,%r1), 0, %r3 +0xda 0x23 0x1f 0xff 0x00 0x00 + +# CHECK: mvcp 4095(%r2,%r15), 0, %r3 +0xda 0x23 0xff 0xff 0x00 0x00 + +# CHECK: mvcp 0(%r2,%r1), 0, %r3 +0xda 0x23 0x10 0x00 0x00 0x00 + +# CHECK: mvcp 0(%r2,%r15), 0, %r3 +0xda 0x23 0xf0 0x00 0x00 0x00 + +# CHECK: mvcs 0(%r0), 0, %r3 +0xdb 0x03 0x00 0x00 0x00 0x00 + +# CHECK: mvcs 0(%r1), 0, %r3 +0xdb 0x13 0x00 0x00 0x00 0x00 + +# CHECK: mvcs 0(%r1), 0(%r1), %r3 +0xdb 0x13 0x00 0x00 0x10 0x00 + +# CHECK: mvcs 0(%r1), 0(%r15), %r3 +0xdb 0x13 0x00 0x00 0xf0 0x00 + +# CHECK: mvcs 0(%r1), 4095, %r3 +0xdb 0x13 0x00 0x00 0x0f 0xff + +# CHECK: mvcs 0(%r1), 4095(%r1), %r3 +0xdb 0x13 0x00 0x00 0x1f 0xff + +# CHECK: mvcs 0(%r1), 4095(%r15), %r3 +0xdb 0x13 0x00 0x00 0xff 0xff + +# CHECK: mvcs 0(%r2,%r1), 0, %r3 +0xdb 0x23 0x10 0x00 0x00 0x00 + +# CHECK: mvcs 0(%r2,%r15), 0, %r3 +0xdb 0x23 0xf0 0x00 0x00 0x00 + +# CHECK: mvcs 4095(%r2,%r1), 0, %r3 +0xdb 0x23 0x1f 0xff 0x00 0x00 + +# CHECK: mvcs 4095(%r2,%r15), 0, %r3 +0xdb 0x23 0xff 0xff 0x00 0x00 + +# CHECK: mvcs 0(%r2,%r1), 0, %r3 +0xdb 0x23 0x10 0x00 0x00 0x00 + +# CHECK: mvcs 0(%r2,%r15), 0, %r3 +0xdb 0x23 0xf0 0x00 0x00 0x00 + +# CHECK: mvcsk 0, 0 +0xe5 0x0e 0x00 0x00 0x00 0x00 + +# CHECK: mvcsk 0(%r1), 0(%r2) +0xe5 0x0e 0x10 0x00 0x20 0x00 + +# CHECK: mvcsk 160(%r1), 320(%r15) +0xe5 0x0e 0x10 0xa0 0xf1 0x40 + +# CHECK: mvcsk 0(%r1), 4095 +0xe5 0x0e 0x10 0x00 0x0f 0xff + +# CHECK: mvcsk 0(%r1), 4095(%r2) +0xe5 0x0e 0x10 0x00 0x2f 0xff + +# CHECK: mvcsk 0(%r1), 4095(%r15) +0xe5 0x0e 0x10 0x00 0xff 0xff + +# CHECK: mvcsk 0(%r1), 0 +0xe5 0x0e 0x10 0x00 0x00 0x00 + +# CHECK: mvcsk 0(%r15), 0 +0xe5 0x0e 0xf0 0x00 0x00 0x00 + +# CHECK: mvcsk 4095(%r1), 0 +0xe5 0x0e 0x1f 0xff 0x00 0x00 + +# CHECK: mvcsk 4095(%r15), 0 +0xe5 0x0e 0xff 0xff 0x00 0x00 + # CHECK: mvghi 0, 0 0xe5 0x48 0x00 0x00 0x00 0x00 @@ -11757,6 +12573,18 @@ # CHECK: mvo 0(1), 0(16,%r15) 0xf1 0x0f 0x00 0x00 0xf0 0x00 +# CHECK: mvpg %r0, %r0 +0xb2 0x54 0x00 0x00 + +# CHECK: mvpg %r0, %r15 +0xb2 0x54 0x00 0x0f + +# CHECK: mvpg %r15, %r0 +0xb2 0x54 0x00 0xf0 + +# CHECK: mvpg %r7, %r8 +0xb2 0x54 0x00 0x78 + # CHECK: mvst %r0, %r0 0xb2 0x55 0x00 0x00 @@ -12687,9 +13515,33 @@ # CHECK: pack 0(1), 0(16,%r15) 0xf2 0x0f 0x00 0x00 0xf0 0x00 +# CHECK: palb +0xb2 0x48 0x00 0x00 + +# CHECK: pc 0 +0xb2 0x18 0x00 0x00 + +# CHECK: pc 0(%r1) +0xb2 0x18 0x10 0x00 + +# CHECK: pc 0(%r15) +0xb2 0x18 0xf0 0x00 + +# CHECK: pc 4095 +0xb2 0x18 0x0f 0xff + +# CHECK: pc 4095(%r1) +0xb2 0x18 0x1f 0xff + +# CHECK: pc 4095(%r15) +0xb2 0x18 0xff 0xff + # CHECK: pcc 0xb9 0x2c 0x00 0x00 +# CHECK: pckmo +0xb9 0x28 0x00 0x00 + # CHECK: pfd 0, -524288 0xe3 0x00 0x00 0x00 0x80 0x36 @@ -12720,9 +13572,54 @@ # CHECK: pfd 15, 0 0xe3 0xf0 0x00 0x00 0x00 0x36 +# CHECK: pfmf %r0, %r0 +0xb9 0xaf 0x00 0x00 + +# CHECK: pfmf %r0, %r15 +0xb9 0xaf 0x00 0x0f + +# CHECK: pfmf %r15, %r0 +0xb9 0xaf 0x00 0xf0 + +# CHECK: pfmf %r7, %r8 +0xb9 0xaf 0x00 0x78 + +# CHECK: pfmf %r15, %r15 +0xb9 0xaf 0x00 0xff + # CHECK: pfpo 0x01 0x0a +# CHECK: pgin %r0, %r0 +0xb2 0x2e 0x00 0x00 + +# CHECK: pgin %r0, %r15 +0xb2 0x2e 0x00 0x0f + +# CHECK: pgin %r15, %r0 +0xb2 0x2e 0x00 0xf0 + +# CHECK: pgin %r7, %r8 +0xb2 0x2e 0x00 0x78 + +# CHECK: pgin %r15, %r15 +0xb2 0x2e 0x00 0xff + +# CHECK: pgout %r0, %r0 +0xb2 0x2f 0x00 0x00 + +# CHECK: pgout %r0, %r15 +0xb2 0x2f 0x00 0x0f + +# CHECK: pgout %r15, %r0 +0xb2 0x2f 0x00 0xf0 + +# CHECK: pgout %r7, %r8 +0xb2 0x2f 0x00 0x78 + +# CHECK: pgout %r15, %r15 +0xb2 0x2f 0x00 0xff + # CHECK: pka 0, 0(1) 0xe9 0x00 0x00 0x00 0x00 0x00 @@ -12846,6 +13743,45 @@ # CHECK: pr 0x01 0x01 +# CHECK: pt %r0, %r0 +0xb2 0x28 0x00 0x00 + +# CHECK: pt %r0, %r15 +0xb2 0x28 0x00 0x0f + +# CHECK: pt %r15, %r0 +0xb2 0x28 0x00 0xf0 + +# CHECK: pt %r7, %r8 +0xb2 0x28 0x00 0x78 + +# CHECK: ptf %r0 +0xb9 0xa2 0x00 0x00 + +# CHECK: ptf %r1 +0xb9 0xa2 0x00 0x10 + +# CHECK: ptf %r15 +0xb9 0xa2 0x00 0xf0 + +# CHECK: ptff +0x01 0x04 + +# CHECK: pti %r0, %r0 +0xb9 0x9e 0x00 0x00 + +# CHECK: pti %r0, %r15 +0xb9 0x9e 0x00 0x0f + +# CHECK: pti %r15, %r0 +0xb9 0x9e 0x00 0xf0 + +# CHECK: pti %r7, %r8 +0xb9 0x9e 0x00 0x78 + +# CHECK: ptlb +0xb2 0x0d 0x00 0x00 + # CHECK: qadtr %f0, %f0, %f0, 0 0xb3 0xf5 0x00 0x00 @@ -12882,6 +13818,45 @@ # CHECK: qaxtr %f13, %f0, %f0, 0 0xb3 0xfd 0x00 0xd0 +# CHECK: qctri 0 +0xb2 0x8e 0x00 0x00 + +# CHECK: qctri 0(%r1) +0xb2 0x8e 0x10 0x00 + +# CHECK: qctri 0(%r15) +0xb2 0x8e 0xf0 0x00 + +# CHECK: qctri 4095 +0xb2 0x8e 0x0f 0xff + +# CHECK: qctri 4095(%r1) +0xb2 0x8e 0x1f 0xff + +# CHECK: qctri 4095(%r15) +0xb2 0x8e 0xff 0xff + +# CHECK: qsi 0 +0xb2 0x86 0x00 0x00 + +# CHECK: qsi 0(%r1) +0xb2 0x86 0x10 0x00 + +# CHECK: qsi 0(%r15) +0xb2 0x86 0xf0 0x00 + +# CHECK: qsi 4095 +0xb2 0x86 0x0f 0xff + +# CHECK: qsi 4095(%r1) +0xb2 0x86 0x1f 0xff + +# CHECK: qsi 4095(%r15) +0xb2 0x86 0xff 0xff + +# CHECK: rchp +0xb2 0x3b 0x00 0x00 + # CHECK: risbg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x55 @@ -13080,6 +14055,54 @@ # CHECK: rosbg %r4, %r5, 6, 7, 8 0xec 0x45 0x06 0x07 0x08 0x56 +# CHECK: rp 0 +0xb2 0x77 0x00 0x00 + +# CHECK: rp 0(%r1) +0xb2 0x77 0x10 0x00 + +# CHECK: rp 0(%r15) +0xb2 0x77 0xf0 0x00 + +# CHECK: rp 4095 +0xb2 0x77 0x0f 0xff + +# CHECK: rp 4095(%r1) +0xb2 0x77 0x1f 0xff + +# CHECK: rp 4095(%r15) +0xb2 0x77 0xff 0xff + +# CHECK: rrbe %r0, %r0 +0xb2 0x2a 0x00 0x00 + +# CHECK: rrbe %r0, %r15 +0xb2 0x2a 0x00 0x0f + +# CHECK: rrbe %r15, %r0 +0xb2 0x2a 0x00 0xf0 + +# CHECK: rrbe %r7, %r8 +0xb2 0x2a 0x00 0x78 + +# CHECK: rrbe %r15, %r15 +0xb2 0x2a 0x00 0xff + +# CHECK: rrbm %r0, %r0 +0xb9 0xae 0x00 0x00 + +# CHECK: rrbm %r0, %r15 +0xb9 0xae 0x00 0x0f + +# CHECK: rrbm %r15, %r0 +0xb9 0xae 0x00 0xf0 + +# CHECK: rrbm %r7, %r8 +0xb9 0xae 0x00 0x78 + +# CHECK: rrbm %r15, %r15 +0xb9 0xae 0x00 0xff + # CHECK: rrdtr %f0, %f0, %f0, 0 0xb3 0xf7 0x00 0x00 @@ -13116,6 +14139,9 @@ # CHECK: rrxtr %f13, %f0, %f0, 0 0xb3 0xff 0x00 0xd0 +# CHECK: rsch +0xb2 0x38 0x00 0x00 + # CHECK: rxsbg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x57 @@ -13158,6 +14184,45 @@ # CHECK: s %r15, 0 0x5b 0xf0 0x00 0x00 +# CHECK: sac 0 +0xb2 0x19 0x00 0x00 + +# CHECK: sac 0(%r1) +0xb2 0x19 0x10 0x00 + +# CHECK: sac 0(%r15) +0xb2 0x19 0xf0 0x00 + +# CHECK: sac 4095 +0xb2 0x19 0x0f 0xff + +# CHECK: sac 4095(%r1) +0xb2 0x19 0x1f 0xff + +# CHECK: sac 4095(%r15) +0xb2 0x19 0xff 0xff + +# CHECK: sacf 0 +0xb2 0x79 0x00 0x00 + +# CHECK: sacf 0(%r1) +0xb2 0x79 0x10 0x00 + +# CHECK: sacf 0(%r15) +0xb2 0x79 0xf0 0x00 + +# CHECK: sacf 4095 +0xb2 0x79 0x0f 0xff + +# CHECK: sacf 4095(%r1) +0xb2 0x79 0x1f 0xff + +# CHECK: sacf 4095(%r15) +0xb2 0x79 0xff 0xff + +# CHECK: sal +0xb2 0x37 0x00 0x00 + # CHECK: sam24 0x01 0x0c @@ -13182,6 +14247,60 @@ # CHECK: sar %a15, %r15 0xb2 0x4e 0x00 0xff +# CHECK: scctr %r0, %r0 +0xb2 0xe0 0x00 0x00 + +# CHECK: scctr %r0, %r15 +0xb2 0xe0 0x00 0x0f + +# CHECK: scctr %r15, %r0 +0xb2 0xe0 0x00 0xf0 + +# CHECK: scctr %r7, %r8 +0xb2 0xe0 0x00 0x78 + +# CHECK: schm +0xb2 0x3c 0x00 0x00 + +# CHECK: sck 0 +0xb2 0x04 0x00 0x00 + +# CHECK: sck 0(%r1) +0xb2 0x04 0x10 0x00 + +# CHECK: sck 0(%r15) +0xb2 0x04 0xf0 0x00 + +# CHECK: sck 4095 +0xb2 0x04 0x0f 0xff + +# CHECK: sck 4095(%r1) +0xb2 0x04 0x1f 0xff + +# CHECK: sck 4095(%r15) +0xb2 0x04 0xff 0xff + +# CHECK: sckc 0 +0xb2 0x06 0x00 0x00 + +# CHECK: sckc 0(%r1) +0xb2 0x06 0x10 0x00 + +# CHECK: sckc 0(%r15) +0xb2 0x06 0xf0 0x00 + +# CHECK: sckc 4095 +0xb2 0x06 0x0f 0xff + +# CHECK: sckc 4095(%r1) +0xb2 0x06 0x1f 0xff + +# CHECK: sckc 4095(%r15) +0xb2 0x06 0xff 0xff + +# CHECK: sckpf +0x01 0x07 + # CHECK: sd %f0, 0 0x6b 0x00 0x00 0x00 @@ -13536,6 +14655,72 @@ # CHECK: shy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x7b +# CHECK: sie 0 +0xb2 0x14 0x00 0x00 + +# CHECK: sie 0(%r1) +0xb2 0x14 0x10 0x00 + +# CHECK: sie 0(%r15) +0xb2 0x14 0xf0 0x00 + +# CHECK: sie 4095 +0xb2 0x14 0x0f 0xff + +# CHECK: sie 4095(%r1) +0xb2 0x14 0x1f 0xff + +# CHECK: sie 4095(%r15) +0xb2 0x14 0xff 0xff + +# CHECK: siga 0 +0xb2 0x74 0x00 0x00 + +# CHECK: siga 0(%r1) +0xb2 0x74 0x10 0x00 + +# CHECK: siga 0(%r15) +0xb2 0x74 0xf0 0x00 + +# CHECK: siga 4095 +0xb2 0x74 0x0f 0xff + +# CHECK: siga 4095(%r1) +0xb2 0x74 0x1f 0xff + +# CHECK: siga 4095(%r15) +0xb2 0x74 0xff 0xff + +# CHECK: sigp %r0, %r0, 0 +0xae 0x00 0x00 0x00 + +# CHECK: sigp %r0, %r15, 0 +0xae 0x0f 0x00 0x00 + +# CHECK: sigp %r14, %r15, 0 +0xae 0xef 0x00 0x00 + +# CHECK: sigp %r15, %r15, 0 +0xae 0xff 0x00 0x00 + +# CHECK: sigp %r0, %r0, 4095 +0xae 0x00 0x0f 0xff + +# CHECK: sigp %r0, %r0, 1 +0xae 0x00 0x00 0x01 + +# CHECK: sigp %r0, %r0, 0(%r1) +0xae 0x00 0x10 0x00 + +# CHECK: sigp %r0, %r0, 0(%r15) +0xae 0x00 0xf0 0x00 + +# CHECK: sigp %r0, %r0, 4095(%r1) +0xae 0x00 0x1f 0xff + +# CHECK: sigp %r0, %r0, 4095(%r15) +0xae 0x00 0xff 0xff + # CHECK: sl %r0, 0 0x5f 0x00 0x00 0x00 @@ -14163,6 +15348,36 @@ # CHECK: sp 0(1), 0(16,%r15) 0xfb 0x0f 0x00 0x00 0xf0 0x00 +# CHECK: spctr %r0, %r0 +0xb2 0xe1 0x00 0x00 + +# CHECK: spctr %r0, %r15 +0xb2 0xe1 0x00 0x0f + +# CHECK: spctr %r15, %r0 +0xb2 0xe1 0x00 0xf0 + +# CHECK: spctr %r7, %r8 +0xb2 0xe1 0x00 0x78 + +# CHECK: spka 0 +0xb2 0x0a 0x00 0x00 + +# CHECK: spka 0(%r1) +0xb2 0x0a 0x10 0x00 + +# CHECK: spka 0(%r15) +0xb2 0x0a 0xf0 0x00 + +# CHECK: spka 4095 +0xb2 0x0a 0x0f 0xff + +# CHECK: spka 4095(%r1) +0xb2 0x0a 0x1f 0xff + +# CHECK: spka 4095(%r15) +0xb2 0x0a 0xff 0xff + # CHECK: spm %r0 0x04 0x00 @@ -14172,6 +15387,42 @@ # CHECK: spm %r15 0x04 0xf0 +# CHECK: spt 0 +0xb2 0x08 0x00 0x00 + +# CHECK: spt 0(%r1) +0xb2 0x08 0x10 0x00 + +# CHECK: spt 0(%r15) +0xb2 0x08 0xf0 0x00 + +# CHECK: spt 4095 +0xb2 0x08 0x0f 0xff + +# CHECK: spt 4095(%r1) +0xb2 0x08 0x1f 0xff + +# CHECK: spt 4095(%r15) +0xb2 0x08 0xff 0xff + +# CHECK: spx 0 +0xb2 0x10 0x00 0x00 + +# CHECK: spx 0(%r1) +0xb2 0x10 0x10 0x00 + +# CHECK: spx 0(%r15) +0xb2 0x10 0xf0 0x00 + +# CHECK: spx 4095 +0xb2 0x10 0x0f 0xff + +# CHECK: spx 4095(%r1) +0xb2 0x10 0x1f 0xff + +# CHECK: spx 4095(%r15) +0xb2 0x10 0xff 0xff + # CHECK: sqd %f0, 0 0xed 0x00 0x00 0x00 0x00 0x35 @@ -14757,6 +16008,75 @@ # CHECK: srxt %f13, %f13, 0 0xed 0xd0 0x00 0x00 0xd0 0x49 +# CHECK: ssar %r0 +0xb2 0x25 0x00 0x00 + +# CHECK: ssar %r1 +0xb2 0x25 0x00 0x10 + +# CHECK: ssar %r15 +0xb2 0x25 0x00 0xf0 + +# CHECK: ssair %r0 +0xb9 0x9f 0x00 0x00 + +# CHECK: ssair %r1 +0xb9 0x9f 0x00 0x10 + +# CHECK: ssair %r15 +0xb9 0x9f 0x00 0xf0 + +# CHECK: ssch 0 +0xb2 0x33 0x00 0x00 + +# CHECK: ssch 0(%r1) +0xb2 0x33 0x10 0x00 + +# CHECK: ssch 0(%r15) +0xb2 0x33 0xf0 0x00 + +# CHECK: ssch 4095 +0xb2 0x33 0x0f 0xff + +# CHECK: ssch 4095(%r1) +0xb2 0x33 0x1f 0xff + +# CHECK: ssch 4095(%r15) +0xb2 0x33 0xff 0xff + +# CHECK: sske %r0, %r0 +0xb2 0x2b 0x00 0x00 + +# CHECK: sske %r0, %r15 +0xb2 0x2b 0x00 0x0f + +# CHECK: sske %r15, %r0 +0xb2 0x2b 0x00 0xf0 + +# CHECK: sske %r0, %r0, 15 +0xb2 0x2b 0xf0 0x00 + +# CHECK: sske %r4, %r6, 7 +0xb2 0x2b 0x70 0x46 + +# CHECK: ssm 0 +0x80 0x00 0x00 0x00 + +# CHECK: ssm 0(%r1) +0x80 0x00 0x10 0x00 + +# CHECK: ssm 0(%r15) +0x80 0x00 0xf0 0x00 + +# CHECK: ssm 4095 +0x80 0x00 0x0f 0xff + +# CHECK: ssm 4095(%r1) +0x80 0x00 0x1f 0xff + +# CHECK: ssm 4095(%r15) +0x80 0x00 0xff 0xff + # CHECK: st %r0, 0 0x50 0x00 0x00 0x00 @@ -14847,6 +16167,24 @@ # CHECK: stamy %a0, %a0, 524287(%r15) 0xeb 0x00 0xff 0xff 0x7f 0x9b +# CHECK: stap 0 +0xb2 0x12 0x00 0x00 + +# CHECK: stap 0(%r1) +0xb2 0x12 0x10 0x00 + +# CHECK: stap 0(%r15) +0xb2 0x12 0xf0 0x00 + +# CHECK: stap 4095 +0xb2 0x12 0x0f 0xff + +# CHECK: stap 4095(%r1) +0xb2 0x12 0x1f 0xff + +# CHECK: stap 4095(%r15) +0xb2 0x12 0xff 0xff + # CHECK: stc %r0, 0 0x42 0x00 0x00 0x00 @@ -14916,6 +16254,24 @@ # CHECK: stck 4095(%r15) 0xb2 0x05 0xff 0xff +# CHECK: stckc 0 +0xb2 0x07 0x00 0x00 + +# CHECK: stckc 0(%r1) +0xb2 0x07 0x10 0x00 + +# CHECK: stckc 0(%r15) +0xb2 0x07 0xf0 0x00 + +# CHECK: stckc 4095 +0xb2 0x07 0x0f 0xff + +# CHECK: stckc 4095(%r1) +0xb2 0x07 0x1f 0xff + +# CHECK: stckc 4095(%r15) +0xb2 0x07 0xff 0xff + # CHECK: stcke 0 0xb2 0x78 0x00 0x00 @@ -15033,6 +16389,111 @@ # CHECK: stcmy %r15, 0, 0 0xeb 0xf0 0x00 0x00 0x00 0x2d +# CHECK: stcps 0 +0xb2 0x3a 0x00 0x00 + +# CHECK: stcps 0(%r1) +0xb2 0x3a 0x10 0x00 + +# CHECK: stcps 0(%r15) +0xb2 0x3a 0xf0 0x00 + +# CHECK: stcps 4095 +0xb2 0x3a 0x0f 0xff + +# CHECK: stcps 4095(%r1) +0xb2 0x3a 0x1f 0xff + +# CHECK: stcps 4095(%r15) +0xb2 0x3a 0xff 0xff + +# CHECK: stcrw 0 +0xb2 0x39 0x00 0x00 + +# CHECK: stcrw 0(%r1) +0xb2 0x39 0x10 0x00 + +# CHECK: stcrw 0(%r15) +0xb2 0x39 0xf0 0x00 + +# CHECK: stcrw 4095 +0xb2 0x39 0x0f 0xff + +# CHECK: stcrw 4095(%r1) +0xb2 0x39 0x1f 0xff + +# CHECK: stcrw 4095(%r15) +0xb2 0x39 0xff 0xff + +# CHECK: stctg %c0, %c0, 0 +0xeb 0x00 0x00 0x00 0x00 0x25 + +# CHECK: stctg %c0, %c15, 0 +0xeb 0x0f 0x00 0x00 0x00 0x25 + +# CHECK: stctg %c14, %c15, 0 +0xeb 0xef 0x00 0x00 0x00 0x25 + +# CHECK: stctg %c15, %c15, 0 +0xeb 0xff 0x00 0x00 0x00 0x25 + +# CHECK: stctg %c0, %c0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x25 + +# CHECK: stctg %c0, %c0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x25 + +# CHECK: stctg %c0, %c0, 0 +0xeb 0x00 0x00 0x00 0x00 0x25 + +# CHECK: stctg %c0, %c0, 1 +0xeb 0x00 0x00 0x01 0x00 0x25 + +# CHECK: stctg %c0, %c0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x25 + +# CHECK: stctg %c0, %c0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x25 + +# CHECK: stctg %c0, %c0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x25 + +# CHECK: stctg %c0, %c0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x25 + +# CHECK: stctg %c0, %c0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x25 + +# CHECK: stctl %c0, %c0, 0 +0xb6 0x00 0x00 0x00 + +# CHECK: stctl %c0, %c15, 0 +0xb6 0x0f 0x00 0x00 + +# CHECK: stctl %c14, %c15, 0 +0xb6 0xef 0x00 0x00 + +# CHECK: stctl %c15, %c15, 0 +0xb6 0xff 0x00 0x00 + +# CHECK: stctl %c0, %c0, 4095 +0xb6 0x00 0x0f 0xff + +# CHECK: stctl %c0, %c0, 1 +0xb6 0x00 0x00 0x01 + +# CHECK: stctl %c0, %c0, 0(%r1) +0xb6 0x00 0x10 0x00 + +# CHECK: stctl %c0, %c0, 0(%r15) +0xb6 0x00 0xf0 0x00 + +# CHECK: stctl %c0, %c0, 4095(%r1) +0xb6 0x00 0x1f 0xff + +# CHECK: stctl %c0, %c0, 4095(%r15) +0xb6 0x00 0xff 0xff + # CHECK: stcy %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x72 @@ -15195,6 +16656,24 @@ # CHECK: stfh %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0xcb +# CHECK: stfl 0 +0xb2 0xb1 0x00 0x00 + +# CHECK: stfl 0(%r1) +0xb2 0xb1 0x10 0x00 + +# CHECK: stfl 0(%r15) +0xb2 0xb1 0xf0 0x00 + +# CHECK: stfl 4095 +0xb2 0xb1 0x0f 0xff + +# CHECK: stfl 4095(%r1) +0xb2 0xb1 0x1f 0xff + +# CHECK: stfl 4095(%r15) +0xb2 0xb1 0xff 0xff + # CHECK: stfle 0 0xb2 0xb0 0x00 0x00 @@ -15342,6 +16821,24 @@ # CHECK: sthy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x70 +# CHECK: stidp 0 +0xb2 0x02 0x00 0x00 + +# CHECK: stidp 0(%r1) +0xb2 0x02 0x10 0x00 + +# CHECK: stidp 0(%r15) +0xb2 0x02 0xf0 0x00 + +# CHECK: stidp 4095 +0xb2 0x02 0x0f 0xff + +# CHECK: stidp 4095(%r1) +0xb2 0x02 0x1f 0xff + +# CHECK: stidp 4095(%r15) +0xb2 0x02 0xff 0xff + # CHECK: stm %r0, %r0, 0 0x90 0x00 0x00 0x00 @@ -15489,6 +16986,27 @@ # CHECK: stmy %r0, %r0, 524287(%r15) 0xeb 0x00 0xff 0xff 0x7f 0x90 +# CHECK: stnsm 0, 0 +0xac 0x00 0x00 0x00 + +# CHECK: stnsm 4095, 0 +0xac 0x00 0x0f 0xff + +# CHECK: stnsm 0, 255 +0xac 0xff 0x00 0x00 + +# CHECK: stnsm 0(%r1), 42 +0xac 0x2a 0x10 0x00 + +# CHECK: stnsm 0(%r15), 42 +0xac 0x2a 0xf0 0x00 + +# CHECK: stnsm 4095(%r1), 42 +0xac 0x2a 0x1f 0xff + +# CHECK: stnsm 4095(%r15), 42 +0xac 0x2a 0xff 0xff + # CHECK: stoc %r1, 2(%r3), 0 0xeb 0x10 0x30 0x02 0x00 0xf3 @@ -15585,6 +17103,27 @@ # CHECK: stocg %r1, 2(%r3), 15 0xeb 0x1f 0x30 0x02 0x00 0xe3 +# CHECK: stosm 0, 0 +0xad 0x00 0x00 0x00 + +# CHECK: stosm 4095, 0 +0xad 0x00 0x0f 0xff + +# CHECK: stosm 0, 255 +0xad 0xff 0x00 0x00 + +# CHECK: stosm 0(%r1), 42 +0xad 0x2a 0x10 0x00 + +# CHECK: stosm 0(%r15), 42 +0xad 0x2a 0xf0 0x00 + +# CHECK: stosm 4095(%r1), 42 +0xad 0x2a 0x1f 0xff + +# CHECK: stosm 4095(%r15), 42 +0xad 0x2a 0xff 0xff + # CHECK: stpq %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x8e @@ -15615,6 +17154,42 @@ # CHECK: stpq %r14, 0 0xe3 0xe0 0x00 0x00 0x00 0x8e +# CHECK: stpt 0 +0xb2 0x09 0x00 0x00 + +# CHECK: stpt 0(%r1) +0xb2 0x09 0x10 0x00 + +# CHECK: stpt 0(%r15) +0xb2 0x09 0xf0 0x00 + +# CHECK: stpt 4095 +0xb2 0x09 0x0f 0xff + +# CHECK: stpt 4095(%r1) +0xb2 0x09 0x1f 0xff + +# CHECK: stpt 4095(%r15) +0xb2 0x09 0xff 0xff + +# CHECK: stpx 0 +0xb2 0x11 0x00 0x00 + +# CHECK: stpx 0(%r1) +0xb2 0x11 0x10 0x00 + +# CHECK: stpx 0(%r15) +0xb2 0x11 0xf0 0x00 + +# CHECK: stpx 4095 +0xb2 0x11 0x0f 0xff + +# CHECK: stpx 4095(%r1) +0xb2 0x11 0x1f 0xff + +# CHECK: stpx 4095(%r15) +0xb2 0x11 0xff 0xff + # CHECK: strag 0, 0 0xe5 0x02 0x00 0x00 0x00 0x00 @@ -15723,6 +17298,66 @@ # CHECK: strvh %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x3f +# CHECK: stsch 0 +0xb2 0x34 0x00 0x00 + +# CHECK: stsch 0(%r1) +0xb2 0x34 0x10 0x00 + +# CHECK: stsch 0(%r15) +0xb2 0x34 0xf0 0x00 + +# CHECK: stsch 4095 +0xb2 0x34 0x0f 0xff + +# CHECK: stsch 4095(%r1) +0xb2 0x34 0x1f 0xff + +# CHECK: stsch 4095(%r15) +0xb2 0x34 0xff 0xff + +# CHECK: stsi 0 +0xb2 0x7d 0x00 0x00 + +# CHECK: stsi 0(%r1) +0xb2 0x7d 0x10 0x00 + +# CHECK: stsi 0(%r15) +0xb2 0x7d 0xf0 0x00 + +# CHECK: stsi 4095 +0xb2 0x7d 0x0f 0xff + +# CHECK: stsi 4095(%r1) +0xb2 0x7d 0x1f 0xff + +# CHECK: stsi 4095(%r15) +0xb2 0x7d 0xff 0xff + +# CHECK: stura %r0, %r0 +0xb2 0x46 0x00 0x00 + +# CHECK: stura %r0, %r15 +0xb2 0x46 0x00 0x0f + +# CHECK: stura %r15, %r0 +0xb2 0x46 0x00 0xf0 + +# CHECK: stura %r7, %r8 +0xb2 0x46 0x00 0x78 + +# CHECK: sturg %r0, %r0 +0xb9 0x25 0x00 0x00 + +# CHECK: sturg %r0, %r15 +0xb9 0x25 0x00 0x0f + +# CHECK: sturg %r15, %r0 +0xb9 0x25 0x00 0xf0 + +# CHECK: sturg %r7, %r8 +0xb9 0x25 0x00 0x78 + # CHECK: sty %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x50 @@ -15939,6 +17574,33 @@ # CHECK: tam 0x01 0x0b +# CHECK: tar %a0, %r0 +0xb2 0x4c 0x00 0x00 + +# CHECK: tar %a0, %r15 +0xb2 0x4c 0x00 0x0f + +# CHECK: tar %a15, %r0 +0xb2 0x4c 0x00 0xf0 + +# CHECK: tar %a7, %r8 +0xb2 0x4c 0x00 0x78 + +# CHECK: tb %r0, %r0 +0xb2 0x2c 0x00 0x00 + +# CHECK: tb %r0, %r15 +0xb2 0x2c 0x00 0x0f + +# CHECK: tb %r15, %r0 +0xb2 0x2c 0x00 0xf0 + +# CHECK: tb %r7, %r8 +0xb2 0x2c 0x00 0x78 + +# CHECK: tb %r15, %r15 +0xb2 0x2c 0x00 0xff + # CHECK: tbdr %f0, 0, %f0 0xb3 0x51 0x00 0x00 @@ -16371,6 +18033,54 @@ # CHECK: tp 0(16,%r15) 0xeb 0xf0 0xf0 0x00 0x00 0xc0 +# CHECK: tpi 0 +0xb2 0x36 0x00 0x00 + +# CHECK: tpi 0(%r1) +0xb2 0x36 0x10 0x00 + +# CHECK: tpi 0(%r15) +0xb2 0x36 0xf0 0x00 + +# CHECK: tpi 4095 +0xb2 0x36 0x0f 0xff + +# CHECK: tpi 4095(%r1) +0xb2 0x36 0x1f 0xff + +# CHECK: tpi 4095(%r15) +0xb2 0x36 0xff 0xff + +# CHECK: tprot 0, 0 +0xe5 0x01 0x00 0x00 0x00 0x00 + +# CHECK: tprot 0(%r1), 0(%r2) +0xe5 0x01 0x10 0x00 0x20 0x00 + +# CHECK: tprot 160(%r1), 320(%r15) +0xe5 0x01 0x10 0xa0 0xf1 0x40 + +# CHECK: tprot 0(%r1), 4095 +0xe5 0x01 0x10 0x00 0x0f 0xff + +# CHECK: tprot 0(%r1), 4095(%r2) +0xe5 0x01 0x10 0x00 0x2f 0xff + +# CHECK: tprot 0(%r1), 4095(%r15) +0xe5 0x01 0x10 0x00 0xff 0xff + +# CHECK: tprot 0(%r1), 0 +0xe5 0x01 0x10 0x00 0x00 0x00 + +# CHECK: tprot 0(%r15), 0 +0xe5 0x01 0xf0 0x00 0x00 0x00 + +# CHECK: tprot 4095(%r1), 0 +0xe5 0x01 0x1f 0xff 0x00 0x00 + +# CHECK: tprot 4095(%r15), 0 +0xe5 0x01 0xff 0xff 0x00 0x00 + # CHECK: tr 0(1), 0 0xdc 0x00 0x00 0x00 0x00 0x00 @@ -16407,6 +18117,96 @@ # CHECK: tr 0(256,%r15), 0 0xdc 0xff 0xf0 0x00 0x00 0x00 +# CHECK: trace %r0, %r0, 0 +0x99 0x00 0x00 0x00 + +# CHECK: trace %r0, %r15, 0 +0x99 0x0f 0x00 0x00 + +# CHECK: trace %r14, %r15, 0 +0x99 0xef 0x00 0x00 + +# CHECK: trace %r15, %r15, 0 +0x99 0xff 0x00 0x00 + +# CHECK: trace %r0, %r0, 4095 +0x99 0x00 0x0f 0xff + +# CHECK: trace %r0, %r0, 1 +0x99 0x00 0x00 0x01 + +# CHECK: trace %r0, %r0, 0(%r1) +0x99 0x00 0x10 0x00 + +# CHECK: trace %r0, %r0, 0(%r15) +0x99 0x00 0xf0 0x00 + +# CHECK: trace %r0, %r0, 4095(%r1) +0x99 0x00 0x1f 0xff + +# CHECK: trace %r0, %r0, 4095(%r15) +0x99 0x00 0xff 0xff + +# CHECK: tracg %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x0f + +# CHECK: tracg %r0, %r15, 0 +0xeb 0x0f 0x00 0x00 0x00 0x0f + +# CHECK: tracg %r14, %r15, 0 +0xeb 0xef 0x00 0x00 0x00 0x0f + +# CHECK: tracg %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0x0f + +# CHECK: tracg %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0x0f + +# CHECK: tracg %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0x0f + +# CHECK: tracg %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0x0f + +# CHECK: tracg %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0x0f + +# CHECK: tracg %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0x0f + +# CHECK: tracg %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0x0f + +# CHECK: tracg %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0x0f + +# CHECK: tracg %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0x0f + +# CHECK: tracg %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0x0f + +# CHECK: trap2 +0x01 0xff + +# CHECK: trap4 0 +0xb2 0xff 0x00 0x00 + +# CHECK: trap4 0(%r1) +0xb2 0xff 0x10 0x00 + +# CHECK: trap4 0(%r15) +0xb2 0xff 0xf0 0x00 + +# CHECK: trap4 4095 +0xb2 0xff 0x0f 0xff + +# CHECK: trap4 4095(%r1) +0xb2 0xff 0x1f 0xff + +# CHECK: trap4 4095(%r15) +0xb2 0xff 0xff 0xff + # CHECK: tre %r0, %r0 0xb2 0xa5 0x00 0x00 @@ -16617,6 +18417,24 @@ # CHECK: ts 4095(%r15) 0x93 0x00 0xff 0xff +# CHECK: tsch 0 +0xb2 0x35 0x00 0x00 + +# CHECK: tsch 0(%r1) +0xb2 0x35 0x10 0x00 + +# CHECK: tsch 0(%r15) +0xb2 0x35 0xf0 0x00 + +# CHECK: tsch 4095 +0xb2 0x35 0x0f 0xff + +# CHECK: tsch 4095(%r1) +0xb2 0x35 0x1f 0xff + +# CHECK: tsch 4095(%r15) +0xb2 0x35 0xff 0xff + # CHECK: unpk 0(1), 0(1) 0xf3 0x00 0x00 0x00 0x00 0x00 @@ -16926,6 +18744,9 @@ # CHECK: xrk %r2, %r3, %r4 0xb9 0xf7 0x40 0x23 +# CHECK: xsch +0xb2 0x76 0x00 0x00 + # CHECK: xy %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x57 diff --git a/llvm/test/MC/SystemZ/insn-bad-z196.s b/llvm/test/MC/SystemZ/insn-bad-z196.s index 81cabef7840..33059529f74 100644 --- a/llvm/test/MC/SystemZ/insn-bad-z196.s +++ b/llvm/test/MC/SystemZ/insn-bad-z196.s @@ -608,6 +608,11 @@ clih %r0, -1 clih %r0, (1 << 32) +#CHECK: error: instruction requires: enhanced-dat-2 +#CHECK: crdte %r0, %r0, %r0, 0 + + crdte %r0, %r0, %r0, 0 + #CHECK: error: invalid operand #CHECK: cxfbra %f0, 0, %r0, -1 #CHECK: error: invalid operand diff --git a/llvm/test/MC/SystemZ/insn-bad-zEC12.s b/llvm/test/MC/SystemZ/insn-bad-zEC12.s index 80197a3c1ef..552180a7c61 100644 --- a/llvm/test/MC/SystemZ/insn-bad-zEC12.s +++ b/llvm/test/MC/SystemZ/insn-bad-zEC12.s @@ -162,6 +162,20 @@ cpxt %f0, 0(1), 0 +#CHECK: error: invalid register pair +#CHECK: crdte %r1, %r0, %r0, 0 +#CHECK: error: invalid register pair +#CHECK: crdte %r0, %r0, %r1, 0 +#CHECK: error: invalid operand +#CHECK: crdte %r0, %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: crdte %r0, %r0, %r0, 16 + + crdte %r1, %r0, %r0, 0 + crdte %r0, %r0, %r1, 0 + crdte %r0, %r0, %r0, -1 + crdte %r0, %r0, %r0, 16 + #CHECK: error: instruction requires: dfp-packed-conversion #CHECK: cxpt %f0, 0(1), 0 diff --git a/llvm/test/MC/SystemZ/insn-bad.s b/llvm/test/MC/SystemZ/insn-bad.s index f7a2a378930..57c69f60361 100644 --- a/llvm/test/MC/SystemZ/insn-bad.s +++ b/llvm/test/MC/SystemZ/insn-bad.s @@ -2007,6 +2007,16 @@ csg %r0, %r0, 524288 csg %r0, %r0, 0(%r1,%r2) +#CHECK: error: invalid register pair +#CHECK: csp %r1, %r0 + + csp %r1, %r0 + +#CHECK: error: invalid register pair +#CHECK: cspg %r1, %r0 + + cspg %r1, %r0 + #CHECK: error: invalid use of indexed addressing #CHECK: csst 160(%r1,%r15), 160(%r15), %r2 #CHECK: error: invalid operand @@ -2375,6 +2385,17 @@ deb %f0, 4096 #CHECK: error: invalid operand +#CHECK: diag %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: diag %r0, %r0, 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: diag %r0, %r0, 0(%r1,%r2) + + diag %r0, %r0, -1 + diag %r0, %r0, 4096 + diag %r0, %r0, 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: didbr %f0, %f0, %f0, -1 #CHECK: error: invalid operand #CHECK: didbr %f0, %f0, %f0, 16 @@ -2669,6 +2690,11 @@ eextr %f2, %f0 #CHECK: error: invalid register pair +#CHECK: esta %r1, %r0 + + esta %r1, %r0 + +#CHECK: error: invalid register pair #CHECK: esxtr %f0, %f2 #CHECK: error: invalid register pair #CHECK: esxtr %f2, %f0 @@ -2834,6 +2860,14 @@ icy %r0, -524289 icy %r0, 524288 +#CHECK: error: invalid operand +#CHECK: idte %r0, %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: idte %r0, %r0, %r0, 16 + + idte %r0, %r0, %r0, -1 + idte %r0, %r0, %r0, 16 + #CHECK: error: invalid register pair #CHECK: iextr %f0, %f0, %f2 #CHECK: error: invalid register pair @@ -2894,6 +2928,14 @@ iill %r0, 0x10000 #CHECK: error: invalid operand +#CHECK: ipte %r0, %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: ipte %r0, %r0, %r0, 16 + + ipte %r0, %r0, %r0, -1 + ipte %r0, %r0, %r0, 16 + +#CHECK: error: invalid operand #CHECK: kdb %f0, -1 #CHECK: error: invalid operand #CHECK: kdb %f0, 4096 @@ -3068,6 +3110,23 @@ larl %r0, 1 larl %r0, 0x100000000 +#CHECK: error: invalid use of indexed addressing +#CHECK: lasp 160(%r1,%r15),160(%r15) +#CHECK: error: invalid operand +#CHECK: lasp -1(%r1),160(%r15) +#CHECK: error: invalid operand +#CHECK: lasp 4096(%r1),160(%r15) +#CHECK: error: invalid operand +#CHECK: lasp 0(%r1),-1(%r15) +#CHECK: error: invalid operand +#CHECK: lasp 0(%r1),4096(%r15) + + lasp 160(%r1,%r15),160(%r15) + lasp -1(%r1),160(%r15) + lasp 4096(%r1),160(%r15) + lasp 0(%r1),-1(%r15) + lasp 0(%r1),4096(%r15) + #CHECK: error: instruction requires: interlocked-access1 #CHECK: lax %r1, %r2, 100(%r3) lax %r1, %r2, 100(%r3) @@ -3097,6 +3156,39 @@ lbh %r0, 0 +#CHECK: error: invalid operand +#CHECK: lcctl -1 +#CHECK: error: invalid operand +#CHECK: lcctl 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: lcctl 0(%r1,%r2) + + lcctl -1 + lcctl 4096 + lcctl 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: lctl %c0, %c0, -1 +#CHECK: error: invalid operand +#CHECK: lctl %c0, %c0, 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: lctl %c0, %c0, 0(%r1,%r2) + + lctl %c0, %c0, -1 + lctl %c0, %c0, 4096 + lctl %c0, %c0, 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: lctlg %c0, %c0, -524289 +#CHECK: error: invalid operand +#CHECK: lctlg %c0, %c0, 524288 +#CHECK: error: invalid use of indexed addressing +#CHECK: lctlg %c0, %c0, 0(%r1,%r2) + + lctlg %c0, %c0, -524289 + lctlg %c0, %c0, 524288 + lctlg %c0, %c0, 0(%r1,%r2) + #CHECK: error: invalid register pair #CHECK: lcxbr %f0, %f2 #CHECK: error: invalid register pair @@ -3624,6 +3716,17 @@ lnxr %f0, %f2 lnxr %f2, %f0 +#CHECK: error: invalid operand +#CHECK: lpctl -1 +#CHECK: error: invalid operand +#CHECK: lpctl 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: lpctl 0(%r1,%r2) + + lpctl -1 + lpctl 4096 + lpctl 0(%r1,%r2) + #CHECK: error: instruction requires: interlocked-access1 #CHECK: lpd %r0, 0, 0 lpd %r0, 0, 0 @@ -3632,6 +3735,17 @@ #CHECK: lpdg %r0, 0, 0 lpdg %r0, 0, 0 +#CHECK: error: invalid operand +#CHECK: lpp -1 +#CHECK: error: invalid operand +#CHECK: lpp 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: lpp 0(%r1,%r2) + + lpp -1 + lpp 4096 + lpp 0(%r1,%r2) + #CHECK: error: invalid register pair #CHECK: lpq %r1, 0 #CHECK: error: invalid operand @@ -3643,6 +3757,36 @@ lpq %r0, -524289 lpq %r0, 524288 +#CHECK: error: invalid operand +#CHECK: lptea %r0, %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: lptea %r0, %r0, %r0, 16 + + lptea %r0, %r0, %r0, -1 + lptea %r0, %r0, %r0, 16 + +#CHECK: error: invalid operand +#CHECK: lpsw -1 +#CHECK: error: invalid operand +#CHECK: lpsw 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: lpsw 0(%r1,%r2) + + lpsw -1 + lpsw 4096 + lpsw 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: lpswe -1 +#CHECK: error: invalid operand +#CHECK: lpswe 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: lpswe 0(%r1,%r2) + + lpswe -1 + lpswe 4096 + lpswe 0(%r1,%r2) + #CHECK: error: invalid register pair #CHECK: lpxbr %f0, %f2 #CHECK: error: invalid register pair @@ -3659,6 +3803,30 @@ lpxr %f0, %f2 lpxr %f2, %f0 +#CHECK: error: invalid operand +#CHECK: lra %r0, -1 +#CHECK: error: invalid operand +#CHECK: lra %r0, 4096 + + lra %r0, -1 + lra %r0, 4096 + +#CHECK: error: invalid operand +#CHECK: lrag %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lrag %r0, 524288 + + lrag %r0, -524289 + lrag %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: lray %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lray %r0, 524288 + + lray %r0, -524289 + lray %r0, 524288 + #CHECK: error: invalid register pair #CHECK: lrdr %f0, %f2 @@ -3695,6 +3863,17 @@ lrvg %r0, 524288 #CHECK: error: invalid operand +#CHECK: lsctl -1 +#CHECK: error: invalid operand +#CHECK: lsctl 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: lsctl 0(%r1,%r2) + + lsctl -1 + lsctl 4096 + lsctl 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: lt %r0, -524289 #CHECK: error: invalid operand #CHECK: lt %r0, 524288 @@ -4139,6 +4318,17 @@ ms %r0, 4096 #CHECK: error: invalid operand +#CHECK: msch -1 +#CHECK: error: invalid operand +#CHECK: msch 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: msch 0(%r1,%r2) + + msch -1 + msch 4096 + msch 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: msd %f0, %f0, -1 #CHECK: error: invalid operand #CHECK: msd %f0, %f0, 4096 @@ -4202,6 +4392,11 @@ msgfi %r0, (-1 << 31) - 1 msgfi %r0, (1 << 31) +#CHECK: error: invalid register pair +#CHECK: msta %r1 + + msta %r1 + #CHECK: error: invalid operand #CHECK: msy %r0, -524289 #CHECK: error: invalid operand @@ -4254,6 +4449,23 @@ mvc 0(1,%r2), 0(%r1,%r2) mvc 0(-), 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: mvcdk 160(%r1,%r15),160(%r15) +#CHECK: error: invalid operand +#CHECK: mvcdk -1(%r1),160(%r15) +#CHECK: error: invalid operand +#CHECK: mvcdk 4096(%r1),160(%r15) +#CHECK: error: invalid operand +#CHECK: mvcdk 0(%r1),-1(%r15) +#CHECK: error: invalid operand +#CHECK: mvcdk 0(%r1),4096(%r15) + + mvcdk 160(%r1,%r15),160(%r15) + mvcdk -1(%r1),160(%r15) + mvcdk 4096(%r1),160(%r15) + mvcdk 0(%r1),-1(%r15) + mvcdk 0(%r1),4096(%r15) + #CHECK: error: missing length in address #CHECK: mvcin 0, 0 #CHECK: error: missing length in address @@ -4363,6 +4575,98 @@ mvclu %r0, %r0, -524289 mvclu %r0, %r0, 524288 +#CHECK: error: invalid use of indexed addressing +#CHECK: mvcos 160(%r1,%r15), 160(%r15), %r2 +#CHECK: error: invalid operand +#CHECK: mvcos -1(%r1), 160(%r15), %r2 +#CHECK: error: invalid operand +#CHECK: mvcos 4096(%r1), 160(%r15), %r2 +#CHECK: error: invalid operand +#CHECK: mvcos 0(%r1), -1(%r15), %r2 +#CHECK: error: invalid operand +#CHECK: mvcos 0(%r1), 4096(%r15), %r2 + + mvcos 160(%r1,%r15), 160(%r15), %r2 + mvcos -1(%r1), 160(%r15), %r2 + mvcos 4096(%r1), 160(%r15), %r2 + mvcos 0(%r1), -1(%r15), %r2 + mvcos 0(%r1), 4096(%r15), %r2 + +#CHECK: error: invalid use of length addressing +#CHECK: mvcp 0(%r1,%r1), 0(2,%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvcp -1(%r1,%r1), 0(%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvcp 4096(%r1,%r1), 0(%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvcp 0(%r1,%r1), -1(%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvcp 0(%r1,%r1), 4096(%r1), %r3 +#CHECK: error: %r0 used in an address +#CHECK: mvcp 0(%r1,%r0), 0(%r1), %r3 +#CHECK: error: %r0 used in an address +#CHECK: mvcp 0(%r1,%r1), 0(%r0), %r3 +#CHECK: error: invalid use of indexed addressing +#CHECK: mvcp 0(%r1,%r2), 0(%r1,%r2), %r3 +#CHECK: error: unknown token in expression +#CHECK: mvcp 0(-), 0, %r3 + + mvcp 0(%r1,%r1), 0(2,%r1), %r3 + mvcp -1(%r1,%r1), 0(%r1), %r3 + mvcp 4096(%r1,%r1), 0(%r1), %r3 + mvcp 0(%r1,%r1), -1(%r1), %r3 + mvcp 0(%r1,%r1), 4096(%r1), %r3 + mvcp 0(%r1,%r0), 0(%r1), %r3 + mvcp 0(%r1,%r1), 0(%r0), %r3 + mvcp 0(%r1,%r2), 0(%r1,%r2), %r3 + mvcp 0(-), 0, %r3 + +#CHECK: error: invalid use of length addressing +#CHECK: mvcs 0(%r1,%r1), 0(2,%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvcs -1(%r1,%r1), 0(%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvcs 4096(%r1,%r1), 0(%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvcs 0(%r1,%r1), -1(%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvcs 0(%r1,%r1), 4096(%r1), %r3 +#CHECK: error: %r0 used in an address +#CHECK: mvcs 0(%r1,%r0), 0(%r1), %r3 +#CHECK: error: %r0 used in an address +#CHECK: mvcs 0(%r1,%r1), 0(%r0), %r3 +#CHECK: error: invalid use of indexed addressing +#CHECK: mvcs 0(%r1,%r2), 0(%r1,%r2), %r3 +#CHECK: error: unknown token in expression +#CHECK: mvcs 0(-), 0, %r3 + + mvcs 0(%r1,%r1), 0(2,%r1), %r3 + mvcs -1(%r1,%r1), 0(%r1), %r3 + mvcs 4096(%r1,%r1), 0(%r1), %r3 + mvcs 0(%r1,%r1), -1(%r1), %r3 + mvcs 0(%r1,%r1), 4096(%r1), %r3 + mvcs 0(%r1,%r0), 0(%r1), %r3 + mvcs 0(%r1,%r1), 0(%r0), %r3 + mvcs 0(%r1,%r2), 0(%r1,%r2), %r3 + mvcs 0(-), 0, %r3 + +#CHECK: error: invalid use of indexed addressing +#CHECK: mvcsk 160(%r1,%r15),160(%r15) +#CHECK: error: invalid operand +#CHECK: mvcsk -1(%r1),160(%r15) +#CHECK: error: invalid operand +#CHECK: mvcsk 4096(%r1),160(%r15) +#CHECK: error: invalid operand +#CHECK: mvcsk 0(%r1),-1(%r15) +#CHECK: error: invalid operand +#CHECK: mvcsk 0(%r1),4096(%r15) + + mvcsk 160(%r1,%r15),160(%r15) + mvcsk -1(%r1),160(%r15) + mvcsk 4096(%r1),160(%r15) + mvcsk 0(%r1),-1(%r15) + mvcsk 0(%r1),4096(%r15) + #CHECK: error: invalid operand #CHECK: mvghi -1, 0 #CHECK: error: invalid operand @@ -5058,11 +5362,27 @@ pack 0(1,%r2), 0(%r1,%r2) pack 0(-), 0(1) +#CHECK: error: invalid operand +#CHECK: pc -1 +#CHECK: error: invalid operand +#CHECK: pc 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: pc 0(%r1,%r2) + + pc -1 + pc 4096 + pc 0(%r1,%r2) + #CHECK: error: instruction requires: message-security-assist-extension4 #CHECK: pcc pcc +#CHECK: error: instruction requires: message-security-assist-extension3 +#CHECK: pckmo + + pckmo + #CHECK: error: invalid operand #CHECK: pfd -1, 0 #CHECK: error: invalid operand @@ -5237,6 +5557,28 @@ qaxtr %f2, %f0, %f0, 0 #CHECK: error: invalid operand +#CHECK: qctri -1 +#CHECK: error: invalid operand +#CHECK: qctri 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: qctri 0(%r1,%r2) + + qctri -1 + qctri 4096 + qctri 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: qsi -1 +#CHECK: error: invalid operand +#CHECK: qsi 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: qsi 0(%r1,%r2) + + qsi -1 + qsi 4096 + qsi 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,0,-1 #CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,0,64 @@ -5335,6 +5677,22 @@ rosbg %r0,%r0,256,0,0 #CHECK: error: invalid operand +#CHECK: rp -1 +#CHECK: error: invalid operand +#CHECK: rp 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: rp 0(%r1,%r2) + + rp -1 + rp 4096 + rp 0(%r1,%r2) + +#CHECK: error: instruction requires: reset-reference-bits-multiple +#CHECK: rrbm %r0, %r0 + + rrbm %r0, %r0 + +#CHECK: error: invalid operand #CHECK: rrdtr %f0, %f0, %f0, -1 #CHECK: error: invalid operand #CHECK: rrdtr %f0, %f0, %f0, 16 @@ -5388,6 +5746,50 @@ s %r0, 4096 #CHECK: error: invalid operand +#CHECK: sac -1 +#CHECK: error: invalid operand +#CHECK: sac 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: sac 0(%r1,%r2) + + sac -1 + sac 4096 + sac 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: sacf -1 +#CHECK: error: invalid operand +#CHECK: sacf 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: sacf 0(%r1,%r2) + + sacf -1 + sacf 4096 + sacf 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: sck -1 +#CHECK: error: invalid operand +#CHECK: sck 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: sck 0(%r1,%r2) + + sck -1 + sck 4096 + sck 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: sckc -1 +#CHECK: error: invalid operand +#CHECK: sckc 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: sckc 0(%r1,%r2) + + sckc -1 + sckc 4096 + sckc 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: sd %f0, -1 #CHECK: error: invalid operand #CHECK: sd %f0, 4096 @@ -5472,6 +5874,39 @@ shy %r0, 524288 #CHECK: error: invalid operand +#CHECK: sie -1 +#CHECK: error: invalid operand +#CHECK: sie 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: sie 0(%r1,%r2) + + sie -1 + sie 4096 + sie 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: siga -1 +#CHECK: error: invalid operand +#CHECK: siga 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: siga 0(%r1,%r2) + + siga -1 + siga 4096 + siga 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: sigp %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: sigp %r0, %r0, 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: sigp %r0, %r0, 0(%r1,%r2) + + sigp %r0, %r0, -1 + sigp %r0, %r0, 4096 + sigp %r0, %r0, 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: sl %r0, -1 #CHECK: error: invalid operand #CHECK: sl %r0, 4096 @@ -5731,6 +6166,39 @@ sp 0(-), 0(1) #CHECK: error: invalid operand +#CHECK: spka -1 +#CHECK: error: invalid operand +#CHECK: spka 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: spka 0(%r1,%r2) + + spka -1 + spka 4096 + spka 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: spt -1 +#CHECK: error: invalid operand +#CHECK: spt 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: spt 0(%r1,%r2) + + spt -1 + spt 4096 + spt 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: spx -1 +#CHECK: error: invalid operand +#CHECK: spx 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: spx 0(%r1,%r2) + + spx -1 + spx 4096 + spx 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: sqd %f0, -1 #CHECK: error: invalid operand #CHECK: sqd %f0, 4096 @@ -5983,6 +6451,36 @@ srxt %f2, %f0, 0 #CHECK: error: invalid operand +#CHECK: ssch -1 +#CHECK: error: invalid operand +#CHECK: ssch 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: ssch 0(%r1,%r2) + + ssch -1 + ssch 4096 + ssch 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: sske %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: sske %r0, %r0, 16 + + sske %r0, %r0, -1 + sske %r0, %r0, 16 + +#CHECK: error: invalid operand +#CHECK: ssm -1 +#CHECK: error: invalid operand +#CHECK: ssm 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: ssm 0(%r1,%r2) + + ssm -1 + ssm 4096 + ssm 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: st %r0, -1 #CHECK: error: invalid operand #CHECK: st %r0, 4096 @@ -6010,6 +6508,17 @@ stamy %a0, %a0, 0(%r1,%r2) #CHECK: error: invalid operand +#CHECK: stap -1 +#CHECK: error: invalid operand +#CHECK: stap 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stap 0(%r1,%r2) + + stap -1 + stap 4096 + stap 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: stc %r0, -1 #CHECK: error: invalid operand #CHECK: stc %r0, 4096 @@ -6023,6 +6532,50 @@ stch %r0, 0 #CHECK: error: invalid operand +#CHECK: stck -1 +#CHECK: error: invalid operand +#CHECK: stck 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stck 0(%r1,%r2) + + stck -1 + stck 4096 + stck 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: stckc -1 +#CHECK: error: invalid operand +#CHECK: stckc 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stckc 0(%r1,%r2) + + stckc -1 + stckc 4096 + stckc 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: stcke -1 +#CHECK: error: invalid operand +#CHECK: stcke 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stcke 0(%r1,%r2) + + stcke -1 + stcke 4096 + stcke 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: stckf -1 +#CHECK: error: invalid operand +#CHECK: stckf 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stckf 0(%r1,%r2) + + stckf -1 + stckf 4096 + stckf 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: stcm %r0, 0, -1 #CHECK: error: invalid operand #CHECK: stcm %r0, 0, 4096 @@ -6065,6 +6618,50 @@ stcmy %r0, 16, 0 #CHECK: error: invalid operand +#CHECK: stcps -1 +#CHECK: error: invalid operand +#CHECK: stcps 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stcps 0(%r1,%r2) + + stcps -1 + stcps 4096 + stcps 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: stcrw -1 +#CHECK: error: invalid operand +#CHECK: stcrw 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stcrw 0(%r1,%r2) + + stcrw -1 + stcrw 4096 + stcrw 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: stctg %c0, %c0, -524289 +#CHECK: error: invalid operand +#CHECK: stctg %c0, %c0, 524288 +#CHECK: error: invalid use of indexed addressing +#CHECK: stctg %c0, %c0, 0(%r1,%r2) + + stctg %c0, %c0, -524289 + stctg %c0, %c0, 524288 + stctg %c0, %c0, 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: stctl %c0, %c0, -1 +#CHECK: error: invalid operand +#CHECK: stctl %c0, %c0, 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stctl %c0, %c0, 0(%r1,%r2) + + stctl %c0, %c0, -1 + stctl %c0, %c0, 4096 + stctl %c0, %c0, 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: stcy %r0, -524289 #CHECK: error: invalid operand #CHECK: stcy %r0, 524288 @@ -6110,6 +6707,28 @@ stfh %r0, 0 #CHECK: error: invalid operand +#CHECK: stfl -1 +#CHECK: error: invalid operand +#CHECK: stfl 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stfl 0(%r1,%r2) + + stfl -1 + stfl 4096 + stfl 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: stfle -1 +#CHECK: error: invalid operand +#CHECK: stfle 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stfle 0(%r1,%r2) + + stfle -1 + stfle 4096 + stfle 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: stfpc -1 #CHECK: error: invalid operand #CHECK: stfpc 4096 @@ -6178,6 +6797,17 @@ sthy %r0, 524288 #CHECK: error: invalid operand +#CHECK: stidp -1 +#CHECK: error: invalid operand +#CHECK: stidp 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stidp 0(%r1,%r2) + + stidp -1 + stidp 4096 + stidp 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: stm %r0, %r0, 4096 #CHECK: error: invalid use of indexed addressing #CHECK: stm %r0, %r0, 0(%r1,%r2) @@ -6218,6 +6848,51 @@ stmy %r0, %r0, 524288 stmy %r0, %r0, 0(%r1,%r2) +#CHECK: error: invalid operand +#CHECK: stnsm -1, 0 +#CHECK: error: invalid operand +#CHECK: stnsm 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: stnsm 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: stnsm 0, -1 +#CHECK: error: invalid operand +#CHECK: stnsm 0, 256 + + stnsm -1, 0 + stnsm 4096, 0 + stnsm 0(%r1,%r2), 0 + stnsm 0, -1 + stnsm 0, 256 + +#CHECK: error: invalid operand +#CHECK: stosm -1, 0 +#CHECK: error: invalid operand +#CHECK: stosm 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: stosm 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: stosm 0, -1 +#CHECK: error: invalid operand +#CHECK: stosm 0, 256 + + stosm -1, 0 + stosm 4096, 0 + stosm 0(%r1,%r2), 0 + stosm 0, -1 + stosm 0, 256 + +#CHECK: error: invalid operand +#CHECK: stpt -1 +#CHECK: error: invalid operand +#CHECK: stpt 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stpt 0(%r1,%r2) + + stpt -1 + stpt 4096 + stpt 0(%r1,%r2) + #CHECK: error: invalid register pair #CHECK: stpq %r1, 0 #CHECK: error: invalid operand @@ -6229,6 +6904,17 @@ stpq %r0, -524289 stpq %r0, 524288 +#CHECK: error: invalid operand +#CHECK: stpx -1 +#CHECK: error: invalid operand +#CHECK: stpx 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stpx 0(%r1,%r2) + + stpx -1 + stpx 4096 + stpx 0(%r1,%r2) + #CHECK: error: invalid use of indexed addressing #CHECK: strag 160(%r1,%r15),160(%r15) #CHECK: error: invalid operand @@ -6277,6 +6963,28 @@ strvg %r0, 524288 #CHECK: error: invalid operand +#CHECK: stsch -1 +#CHECK: error: invalid operand +#CHECK: stsch 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stsch 0(%r1,%r2) + + stsch -1 + stsch 4096 + stsch 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: stsi -1 +#CHECK: error: invalid operand +#CHECK: stsi 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: stsi 0(%r1,%r2) + + stsi -1 + stsi 4096 + stsi 0(%r1,%r2) + +#CHECK: error: invalid operand #CHECK: sty %r0, -524289 #CHECK: error: invalid operand #CHECK: sty %r0, 524288 @@ -6545,6 +7253,34 @@ tp 0(%r1,%r2) tp 0(-) +#CHECK: error: invalid operand +#CHECK: tpi -1 +#CHECK: error: invalid operand +#CHECK: tpi 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: tpi 0(%r1,%r2) + + tpi -1 + tpi 4096 + tpi 0(%r1,%r2) + +#CHECK: error: invalid use of indexed addressing +#CHECK: tprot 160(%r1,%r15),160(%r15) +#CHECK: error: invalid operand +#CHECK: tprot -1(%r1),160(%r15) +#CHECK: error: invalid operand +#CHECK: tprot 4096(%r1),160(%r15) +#CHECK: error: invalid operand +#CHECK: tprot 0(%r1),-1(%r15) +#CHECK: error: invalid operand +#CHECK: tprot 0(%r1),4096(%r15) + + tprot 160(%r1,%r15),160(%r15) + tprot -1(%r1),160(%r15) + tprot 4096(%r1),160(%r15) + tprot 0(%r1),-1(%r15) + tprot 0(%r1),4096(%r15) + #CHECK: error: missing length in address #CHECK: tr 0, 0 #CHECK: error: missing length in address @@ -6589,6 +7325,39 @@ tr 0(1,%r2), 0(%r1,%r2) tr 0(-), 0 +#CHECK: error: invalid operand +#CHECK: trace %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: trace %r0, %r0, 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: trace %r0, %r0, 0(%r1,%r2) + + trace %r0, %r0, -1 + trace %r0, %r0, 4096 + trace %r0, %r0, 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: tracg %r0, %r0, -524289 +#CHECK: error: invalid operand +#CHECK: tracg %r0, %r0, 524288 +#CHECK: error: invalid use of indexed addressing +#CHECK: tracg %r0, %r0, 0(%r1,%r2) + + tracg %r0, %r0, -524289 + tracg %r0, %r0, 524288 + tracg %r0, %r0, 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: trap4 -1 +#CHECK: error: invalid operand +#CHECK: trap4 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: trap4 0(%r1,%r2) + + trap4 -1 + trap4 4096 + trap4 0(%r1,%r2) + #CHECK: error: invalid register pair #CHECK: tre %r1, %r0 @@ -6759,6 +7528,17 @@ ts 4096 ts 0(%r1,%r2) +#CHECK: error: invalid operand +#CHECK: tsch -1 +#CHECK: error: invalid operand +#CHECK: tsch 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: tsch 0(%r1,%r2) + + tsch -1 + tsch 4096 + tsch 0(%r1,%r2) + #CHECK: error: missing length in address #CHECK: unpk 0, 0(1) #CHECK: error: missing length in address diff --git a/llvm/test/MC/SystemZ/insn-good-z196.s b/llvm/test/MC/SystemZ/insn-good-z196.s index ba56a8ef3cf..a3a66285704 100644 --- a/llvm/test/MC/SystemZ/insn-good-z196.s +++ b/llvm/test/MC/SystemZ/insn-good-z196.s @@ -1761,6 +1761,10 @@ pcc +#CHECK: pckmo # encoding: [0xb9,0x28,0x00,0x00] + + pckmo + #CHECK: popcnt %r0, %r0 # encoding: [0xb9,0xe1,0x00,0x00] #CHECK: popcnt %r0, %r15 # encoding: [0xb9,0xe1,0x00,0x0f] #CHECK: popcnt %r15, %r0 # encoding: [0xb9,0xe1,0x00,0xf0] @@ -1803,6 +1807,18 @@ risblg %r15,%r0,0,0,0 risblg %r4,%r5,6,7,8 +#CHECK: rrbm %r0, %r0 # encoding: [0xb9,0xae,0x00,0x00] +#CHECK: rrbm %r0, %r15 # encoding: [0xb9,0xae,0x00,0x0f] +#CHECK: rrbm %r15, %r0 # encoding: [0xb9,0xae,0x00,0xf0] +#CHECK: rrbm %r7, %r8 # encoding: [0xb9,0xae,0x00,0x78] +#CHECK: rrbm %r15, %r15 # encoding: [0xb9,0xae,0x00,0xff] + + rrbm %r0,%r0 + rrbm %r0,%r15 + rrbm %r15,%r0 + rrbm %r7,%r8 + rrbm %r15,%r15 + #CHECK: sdtra %f0, %f0, %f0, 0 # encoding: [0xb3,0xd3,0x00,0x00] #CHECK: sdtra %f0, %f0, %f0, 15 # encoding: [0xb3,0xd3,0x0f,0x00] #CHECK: sdtra %f0, %f0, %f15, 0 # encoding: [0xb3,0xd3,0xf0,0x00] diff --git a/llvm/test/MC/SystemZ/insn-good-zEC12.s b/llvm/test/MC/SystemZ/insn-good-zEC12.s index 2fe6c46ad90..1f1bfb883bd 100644 --- a/llvm/test/MC/SystemZ/insn-good-zEC12.s +++ b/llvm/test/MC/SystemZ/insn-good-zEC12.s @@ -198,6 +198,20 @@ clgtnl %r0, 0(%r15) clgtnh %r0, 0(%r15) +#CHECK: crdte %r0, %r0, %r0 # encoding: [0xb9,0x8f,0x00,0x00] +#CHECK: crdte %r0, %r0, %r14 # encoding: [0xb9,0x8f,0x00,0x0e] +#CHECK: crdte %r0, %r15, %r0 # encoding: [0xb9,0x8f,0xf0,0x00] +#CHECK: crdte %r14, %r0, %r0 # encoding: [0xb9,0x8f,0x00,0xe0] +#CHECK: crdte %r0, %r0, %r0, 15 # encoding: [0xb9,0x8f,0x0f,0x00] +#CHECK: crdte %r4, %r5, %r6, 7 # encoding: [0xb9,0x8f,0x57,0x46] + + crdte %r0, %r0, %r0 + crdte %r0, %r0, %r14 + crdte %r0, %r15, %r0 + crdte %r14, %r0, %r0 + crdte %r0, %r0, %r0, 15 + crdte %r4, %r5, %r6, 7 + #CHECK: cxzt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xab] #CHECK: cxzt %f13, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xd0,0xab] #CHECK: cxzt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xab] diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s index 73162e4eea7..5b93ef917fd 100644 --- a/llvm/test/MC/SystemZ/insn-good.s +++ b/llvm/test/MC/SystemZ/insn-good.s @@ -741,6 +741,16 @@ ay %r0, 524287(%r15,%r1) ay %r15, 0 +#CHECK: bakr %r0, %r0 # encoding: [0xb2,0x40,0x00,0x00] +#CHECK: bakr %r0, %r15 # encoding: [0xb2,0x40,0x00,0x0f] +#CHECK: bakr %r15, %r0 # encoding: [0xb2,0x40,0x00,0xf0] +#CHECK: bakr %r7, %r8 # encoding: [0xb2,0x40,0x00,0x78] + + bakr %r0,%r0 + bakr %r0,%r15 + bakr %r15,%r0 + bakr %r7,%r8 + #CHECK: bal %r0, 0 # encoding: [0x45,0x00,0x00,0x00] #CHECK: bal %r1, 4095 # encoding: [0x45,0x10,0x0f,0xff] #CHECK: bal %r2, 0(%r1) # encoding: [0x45,0x20,0x10,0x00] @@ -799,6 +809,26 @@ bassm %r14,%r9 bassm %r15,%r1 +#CHECK: bsa %r0, %r0 # encoding: [0xb2,0x5a,0x00,0x00] +#CHECK: bsa %r0, %r15 # encoding: [0xb2,0x5a,0x00,0x0f] +#CHECK: bsa %r15, %r0 # encoding: [0xb2,0x5a,0x00,0xf0] +#CHECK: bsa %r7, %r8 # encoding: [0xb2,0x5a,0x00,0x78] + + bsa %r0,%r0 + bsa %r0,%r15 + bsa %r15,%r0 + bsa %r7,%r8 + +#CHECK: bsg %r0, %r0 # encoding: [0xb2,0x58,0x00,0x00] +#CHECK: bsg %r0, %r15 # encoding: [0xb2,0x58,0x00,0x0f] +#CHECK: bsg %r15, %r0 # encoding: [0xb2,0x58,0x00,0xf0] +#CHECK: bsg %r7, %r8 # encoding: [0xb2,0x58,0x00,0x78] + + bsg %r0,%r0 + bsg %r0,%r15 + bsg %r15,%r0 + bsg %r7,%r8 + #CHECK: bsm %r0, %r1 # encoding: [0x0b,0x01] #CHECK: bsm %r0, %r15 # encoding: [0x0b,0x0f] #CHECK: bsm %r14, %r9 # encoding: [0x0b,0xe9] @@ -6257,6 +6287,10 @@ cs %r0, %r15, 0 cs %r15, %r0, 0 +#CHECK: csch # encoding: [0xb2,0x30,0x00,0x00] + + csch + #CHECK: csdtr %r0, %f0, 0 # encoding: [0xb3,0xe3,0x00,0x00] #CHECK: csdtr %r0, %f15, 0 # encoding: [0xb3,0xe3,0x00,0x0f] #CHECK: csdtr %r0, %f0, 15 # encoding: [0xb3,0xe3,0x0f,0x00] @@ -6293,6 +6327,26 @@ csg %r0, %r15, 0 csg %r15, %r0, 0 +#CHECK: csp %r0, %r0 # encoding: [0xb2,0x50,0x00,0x00] +#CHECK: csp %r0, %r15 # encoding: [0xb2,0x50,0x00,0x0f] +#CHECK: csp %r14, %r0 # encoding: [0xb2,0x50,0x00,0xe0] +#CHECK: csp %r6, %r8 # encoding: [0xb2,0x50,0x00,0x68] + + csp %r0,%r0 + csp %r0,%r15 + csp %r14,%r0 + csp %r6,%r8 + +#CHECK: cspg %r0, %r0 # encoding: [0xb9,0x8a,0x00,0x00] +#CHECK: cspg %r0, %r15 # encoding: [0xb9,0x8a,0x00,0x0f] +#CHECK: cspg %r14, %r0 # encoding: [0xb9,0x8a,0x00,0xe0] +#CHECK: cspg %r6, %r8 # encoding: [0xb9,0x8a,0x00,0x68] + + cspg %r0,%r0 + cspg %r0,%r15 + cspg %r14,%r0 + cspg %r6,%r8 + #CHECK: csst 0, 0, %r0 # encoding: [0xc8,0x02,0x00,0x00,0x00,0x00] #CHECK: csst 0(%r1), 0(%r15), %r2 # encoding: [0xc8,0x22,0x10,0x00,0xf0,0x00] #CHECK: csst 1(%r1), 0(%r15), %r2 # encoding: [0xc8,0x22,0x10,0x01,0xf0,0x00] @@ -6869,6 +6923,28 @@ der %f7, %f8 der %f15, %f0 +#CHECK: diag %r0, %r0, 0 # encoding: [0x83,0x00,0x00,0x00] +#CHECK: diag %r0, %r15, 0 # encoding: [0x83,0x0f,0x00,0x00] +#CHECK: diag %r14, %r15, 0 # encoding: [0x83,0xef,0x00,0x00] +#CHECK: diag %r15, %r15, 0 # encoding: [0x83,0xff,0x00,0x00] +#CHECK: diag %r0, %r0, 4095 # encoding: [0x83,0x00,0x0f,0xff] +#CHECK: diag %r0, %r0, 1 # encoding: [0x83,0x00,0x00,0x01] +#CHECK: diag %r0, %r0, 0(%r1) # encoding: [0x83,0x00,0x10,0x00] +#CHECK: diag %r0, %r0, 0(%r15) # encoding: [0x83,0x00,0xf0,0x00] +#CHECK: diag %r0, %r0, 4095(%r1) # encoding: [0x83,0x00,0x1f,0xff] +#CHECK: diag %r0, %r0, 4095(%r15) # encoding: [0x83,0x00,0xff,0xff] + + diag %r0,%r0,0 + diag %r0,%r15,0 + diag %r14,%r15,0 + diag %r15,%r15,0 + diag %r0,%r0,4095 + diag %r0,%r0,1 + diag %r0,%r0,0(%r1) + diag %r0,%r0,0(%r15) + diag %r0,%r0,4095(%r1) + diag %r0,%r0,4095(%r15) + #CHECK: didbr %f0, %f0, %f0, 0 # encoding: [0xb3,0x5b,0x00,0x00] #CHECK: didbr %f0, %f0, %f0, 15 # encoding: [0xb3,0x5b,0x0f,0x00] #CHECK: didbr %f0, %f0, %f15, 0 # encoding: [0xb3,0x5b,0x00,0x0f] @@ -7137,6 +7213,26 @@ ecag %r0,%r0,524287(%r1) ecag %r0,%r0,524287(%r15) +#CHECK: ecctr %r0, %r0 # encoding: [0xb2,0xe4,0x00,0x00] +#CHECK: ecctr %r0, %r15 # encoding: [0xb2,0xe4,0x00,0x0f] +#CHECK: ecctr %r15, %r0 # encoding: [0xb2,0xe4,0x00,0xf0] +#CHECK: ecctr %r7, %r8 # encoding: [0xb2,0xe4,0x00,0x78] + + ecctr %r0,%r0 + ecctr %r0,%r15 + ecctr %r15,%r0 + ecctr %r7,%r8 + +#CHECK: ecpga %r0, %r0 # encoding: [0xb2,0xed,0x00,0x00] +#CHECK: ecpga %r0, %r15 # encoding: [0xb2,0xed,0x00,0x0f] +#CHECK: ecpga %r15, %r0 # encoding: [0xb2,0xed,0x00,0xf0] +#CHECK: ecpga %r7, %r8 # encoding: [0xb2,0xed,0x00,0x78] + + ecpga %r0,%r0 + ecpga %r0,%r15 + ecpga %r15,%r0 + ecpga %r7,%r8 + #CHECK: ectg 0, 0, %r0 # encoding: [0xc8,0x01,0x00,0x00,0x00,0x00] #CHECK: ectg 0(%r1), 0(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x00,0xf0,0x00] #CHECK: ectg 1(%r1), 0(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x01,0xf0,0x00] @@ -7231,6 +7327,32 @@ efpc %r1 efpc %r15 +#CHECK: epar %r0 # encoding: [0xb2,0x26,0x00,0x00] +#CHECK: epar %r1 # encoding: [0xb2,0x26,0x00,0x10] +#CHECK: epar %r15 # encoding: [0xb2,0x26,0x00,0xf0] + + epar %r0 + epar %r1 + epar %r15 + +#CHECK: epair %r0 # encoding: [0xb9,0x9a,0x00,0x00] +#CHECK: epair %r1 # encoding: [0xb9,0x9a,0x00,0x10] +#CHECK: epair %r15 # encoding: [0xb9,0x9a,0x00,0xf0] + + epair %r0 + epair %r1 + epair %r15 + +#CHECK: epctr %r0, %r0 # encoding: [0xb2,0xe5,0x00,0x00] +#CHECK: epctr %r0, %r15 # encoding: [0xb2,0xe5,0x00,0x0f] +#CHECK: epctr %r15, %r0 # encoding: [0xb2,0xe5,0x00,0xf0] +#CHECK: epctr %r7, %r8 # encoding: [0xb2,0xe5,0x00,0x78] + + epctr %r0,%r0 + epctr %r0,%r15 + epctr %r15,%r0 + epctr %r7,%r8 + #CHECK: epsw %r0, %r8 # encoding: [0xb9,0x8d,0x00,0x08] #CHECK: epsw %r0, %r15 # encoding: [0xb9,0x8d,0x00,0x0f] #CHECK: epsw %r15, %r0 # encoding: [0xb9,0x8d,0x00,0xf0] @@ -7241,6 +7363,42 @@ epsw %r15, %r0 epsw %r15, %r8 +#CHECK: ereg %r0, %r0 # encoding: [0xb2,0x49,0x00,0x00] +#CHECK: ereg %r0, %r15 # encoding: [0xb2,0x49,0x00,0x0f] +#CHECK: ereg %r15, %r0 # encoding: [0xb2,0x49,0x00,0xf0] +#CHECK: ereg %r7, %r8 # encoding: [0xb2,0x49,0x00,0x78] + + ereg %r0,%r0 + ereg %r0,%r15 + ereg %r15,%r0 + ereg %r7,%r8 + +#CHECK: eregg %r0, %r0 # encoding: [0xb9,0x0e,0x00,0x00] +#CHECK: eregg %r0, %r15 # encoding: [0xb9,0x0e,0x00,0x0f] +#CHECK: eregg %r15, %r0 # encoding: [0xb9,0x0e,0x00,0xf0] +#CHECK: eregg %r7, %r8 # encoding: [0xb9,0x0e,0x00,0x78] + + eregg %r0,%r0 + eregg %r0,%r15 + eregg %r15,%r0 + eregg %r7,%r8 + +#CHECK: esar %r0 # encoding: [0xb2,0x27,0x00,0x00] +#CHECK: esar %r1 # encoding: [0xb2,0x27,0x00,0x10] +#CHECK: esar %r15 # encoding: [0xb2,0x27,0x00,0xf0] + + esar %r0 + esar %r1 + esar %r15 + +#CHECK: esair %r0 # encoding: [0xb9,0x9b,0x00,0x00] +#CHECK: esair %r1 # encoding: [0xb9,0x9b,0x00,0x10] +#CHECK: esair %r15 # encoding: [0xb9,0x9b,0x00,0xf0] + + esair %r0 + esair %r1 + esair %r15 + #CHECK: esdtr %f0, %f9 # encoding: [0xb3,0xe7,0x00,0x09] #CHECK: esdtr %f0, %f15 # encoding: [0xb3,0xe7,0x00,0x0f] #CHECK: esdtr %f15, %f0 # encoding: [0xb3,0xe7,0x00,0xf0] @@ -7251,6 +7409,24 @@ esdtr %f15,%f0 esdtr %f15,%f9 +#CHECK: esea %r0 # encoding: [0xb9,0x9d,0x00,0x00] +#CHECK: esea %r1 # encoding: [0xb9,0x9d,0x00,0x10] +#CHECK: esea %r15 # encoding: [0xb9,0x9d,0x00,0xf0] + + esea %r0 + esea %r1 + esea %r15 + +#CHECK: esta %r0, %r0 # encoding: [0xb2,0x4a,0x00,0x00] +#CHECK: esta %r0, %r15 # encoding: [0xb2,0x4a,0x00,0x0f] +#CHECK: esta %r14, %r0 # encoding: [0xb2,0x4a,0x00,0xe0] +#CHECK: esta %r6, %r8 # encoding: [0xb2,0x4a,0x00,0x68] + + esta %r0,%r0 + esta %r0,%r15 + esta %r14,%r0 + esta %r6,%r8 + #CHECK: esxtr %f0, %f8 # encoding: [0xb3,0xef,0x00,0x08] #CHECK: esxtr %f0, %f13 # encoding: [0xb3,0xef,0x00,0x0d] #CHECK: esxtr %f13, %f0 # encoding: [0xb3,0xef,0x00,0xd0] @@ -7438,6 +7614,18 @@ her %f7, %f8 her %f15, %f0 +#CHECK: hsch # encoding: [0xb2,0x31,0x00,0x00] + + hsch + +#CHECK: iac %r0 # encoding: [0xb2,0x24,0x00,0x00] +#CHECK: iac %r1 # encoding: [0xb2,0x24,0x00,0x10] +#CHECK: iac %r15 # encoding: [0xb2,0x24,0x00,0xf0] + + iac %r0 + iac %r1 + iac %r15 + #CHECK: ic %r0, 0 # encoding: [0x43,0x00,0x00,0x00] #CHECK: ic %r0, 4095 # encoding: [0x43,0x00,0x0f,0xff] #CHECK: ic %r0, 0(%r1) # encoding: [0x43,0x00,0x10,0x00] @@ -7536,6 +7724,20 @@ icy %r0, 524287(%r15,%r1) icy %r15, 0 +#CHECK: idte %r0, %r0, %r0 # encoding: [0xb9,0x8e,0x00,0x00] +#CHECK: idte %r0, %r0, %r15 # encoding: [0xb9,0x8e,0x00,0x0f] +#CHECK: idte %r0, %r15, %r0 # encoding: [0xb9,0x8e,0xf0,0x00] +#CHECK: idte %r15, %r0, %r0 # encoding: [0xb9,0x8e,0x00,0xf0] +#CHECK: idte %r0, %r0, %r0, 15 # encoding: [0xb9,0x8e,0x0f,0x00] +#CHECK: idte %r4, %r5, %r6, 7 # encoding: [0xb9,0x8e,0x57,0x46] + + idte %r0, %r0, %r0 + idte %r0, %r0, %r15 + idte %r0, %r15, %r0 + idte %r15, %r0, %r0 + idte %r0, %r0, %r0, 15 + idte %r4, %r5, %r6, 7 + #CHECK: iedtr %f0, %f0, %f0 # encoding: [0xb3,0xf6,0x00,0x00] #CHECK: iedtr %f0, %f0, %f15 # encoding: [0xb3,0xf6,0x00,0x0f] #CHECK: iedtr %f0, %f15, %f0 # encoding: [0xb3,0xf6,0xf0,0x00] @@ -7620,6 +7822,10 @@ iill %r0, 0xffff iill %r15, 0 +#CHECK: ipk # encoding: [0xb2,0x0b,0x00,0x00] + + ipk + #CHECK: ipm %r0 # encoding: [0xb2,0x22,0x00,0x00] #CHECK: ipm %r1 # encoding: [0xb2,0x22,0x00,0x10] #CHECK: ipm %r15 # encoding: [0xb2,0x22,0x00,0xf0] @@ -7628,6 +7834,40 @@ ipm %r1 ipm %r15 +#CHECK: ipte %r0, %r0 # encoding: [0xb2,0x21,0x00,0x00] +#CHECK: ipte %r0, %r15 # encoding: [0xb2,0x21,0x00,0x0f] +#CHECK: ipte %r15, %r0 # encoding: [0xb2,0x21,0x00,0xf0] +#CHECK: ipte %r0, %r0, %r15 # encoding: [0xb2,0x21,0xf0,0x00] +#CHECK: ipte %r0, %r0, %r0, 15 # encoding: [0xb2,0x21,0x0f,0x00] +#CHECK: ipte %r7, %r8, %r9, 10 # encoding: [0xb2,0x21,0x9a,0x78] + + ipte %r0, %r0 + ipte %r0, %r15 + ipte %r15, %r0 + ipte %r0, %r0, %r15 + ipte %r0, %r0, %r0, 15 + ipte %r7, %r8, %r9, 10 + +#CHECK: iske %r0, %r0 # encoding: [0xb2,0x29,0x00,0x00] +#CHECK: iske %r0, %r15 # encoding: [0xb2,0x29,0x00,0x0f] +#CHECK: iske %r15, %r0 # encoding: [0xb2,0x29,0x00,0xf0] +#CHECK: iske %r7, %r8 # encoding: [0xb2,0x29,0x00,0x78] + + iske %r0,%r0 + iske %r0,%r15 + iske %r15,%r0 + iske %r7,%r8 + +#CHECK: ivsk %r0, %r0 # encoding: [0xb2,0x23,0x00,0x00] +#CHECK: ivsk %r0, %r15 # encoding: [0xb2,0x23,0x00,0x0f] +#CHECK: ivsk %r15, %r0 # encoding: [0xb2,0x23,0x00,0xf0] +#CHECK: ivsk %r7, %r8 # encoding: [0xb2,0x23,0x00,0x78] + + ivsk %r0,%r0 + ivsk %r0,%r15 + ivsk %r15,%r0 + ivsk %r7,%r8 + #CHECK: kdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x18] #CHECK: kdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x18] #CHECK: kdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x18] @@ -7917,6 +8157,28 @@ larl %r7,frob@PLT larl %r8,frob@PLT +#CHECK: lasp 0, 0 # encoding: [0xe5,0x00,0x00,0x00,0x00,0x00] +#CHECK: lasp 0(%r1), 0(%r2) # encoding: [0xe5,0x00,0x10,0x00,0x20,0x00] +#CHECK: lasp 160(%r1), 320(%r15) # encoding: [0xe5,0x00,0x10,0xa0,0xf1,0x40] +#CHECK: lasp 0(%r1), 4095 # encoding: [0xe5,0x00,0x10,0x00,0x0f,0xff] +#CHECK: lasp 0(%r1), 4095(%r2) # encoding: [0xe5,0x00,0x10,0x00,0x2f,0xff] +#CHECK: lasp 0(%r1), 4095(%r15) # encoding: [0xe5,0x00,0x10,0x00,0xff,0xff] +#CHECK: lasp 0(%r1), 0 # encoding: [0xe5,0x00,0x10,0x00,0x00,0x00] +#CHECK: lasp 0(%r15), 0 # encoding: [0xe5,0x00,0xf0,0x00,0x00,0x00] +#CHECK: lasp 4095(%r1), 0 # encoding: [0xe5,0x00,0x1f,0xff,0x00,0x00] +#CHECK: lasp 4095(%r15), 0 # encoding: [0xe5,0x00,0xff,0xff,0x00,0x00] + + lasp 0, 0 + lasp 0(%r1), 0(%r2) + lasp 160(%r1), 320(%r15) + lasp 0(%r1), 4095 + lasp 0(%r1), 4095(%r2) + lasp 0(%r1), 4095(%r15) + lasp 0(%r1), 0 + lasp 0(%r15), 0 + lasp 4095(%r1), 0 + lasp 4095(%r15), 0 + #CHECK: lay %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x71] #CHECK: lay %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x71] #CHECK: lay %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x71] @@ -7969,6 +8231,20 @@ lbr %r7, %r8 lbr %r15, %r0 +#CHECK: lcctl 0 # encoding: [0xb2,0x84,0x00,0x00] +#CHECK: lcctl 0(%r1) # encoding: [0xb2,0x84,0x10,0x00] +#CHECK: lcctl 0(%r15) # encoding: [0xb2,0x84,0xf0,0x00] +#CHECK: lcctl 4095 # encoding: [0xb2,0x84,0x0f,0xff] +#CHECK: lcctl 4095(%r1) # encoding: [0xb2,0x84,0x1f,0xff] +#CHECK: lcctl 4095(%r15) # encoding: [0xb2,0x84,0xff,0xff] + + lcctl 0 + lcctl 0(%r1) + lcctl 0(%r15) + lcctl 4095 + lcctl 4095(%r1) + lcctl 4095(%r15) + #CHECK: lcdbr %f0, %f9 # encoding: [0xb3,0x13,0x00,0x09] #CHECK: lcdbr %f0, %f15 # encoding: [0xb3,0x13,0x00,0x0f] #CHECK: lcdbr %f15, %f0 # encoding: [0xb3,0x13,0x00,0xf0] @@ -8039,6 +8315,56 @@ lcr %r15,%r0 lcr %r7,%r8 +#CHECK: lctl %c0, %c0, 0 # encoding: [0xb7,0x00,0x00,0x00] +#CHECK: lctl %c0, %c15, 0 # encoding: [0xb7,0x0f,0x00,0x00] +#CHECK: lctl %c14, %c15, 0 # encoding: [0xb7,0xef,0x00,0x00] +#CHECK: lctl %c15, %c15, 0 # encoding: [0xb7,0xff,0x00,0x00] +#CHECK: lctl %c0, %c0, 4095 # encoding: [0xb7,0x00,0x0f,0xff] +#CHECK: lctl %c0, %c0, 1 # encoding: [0xb7,0x00,0x00,0x01] +#CHECK: lctl %c0, %c0, 0(%r1) # encoding: [0xb7,0x00,0x10,0x00] +#CHECK: lctl %c0, %c0, 0(%r15) # encoding: [0xb7,0x00,0xf0,0x00] +#CHECK: lctl %c0, %c0, 4095(%r1) # encoding: [0xb7,0x00,0x1f,0xff] +#CHECK: lctl %c0, %c0, 4095(%r15) # encoding: [0xb7,0x00,0xff,0xff] + + lctl %c0,%c0,0 + lctl %c0,%c15,0 + lctl %c14,%c15,0 + lctl %c15,%c15,0 + lctl %c0,%c0,4095 + lctl %c0,%c0,1 + lctl %c0,%c0,0(%r1) + lctl %c0,%c0,0(%r15) + lctl %c0,%c0,4095(%r1) + lctl %c0,%c0,4095(%r15) + +#CHECK: lctlg %c0, %c0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x2f] +#CHECK: lctlg %c0, %c15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x2f] +#CHECK: lctlg %c14, %c15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x2f] +#CHECK: lctlg %c15, %c15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x2f] +#CHECK: lctlg %c0, %c0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x2f] +#CHECK: lctlg %c0, %c0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x2f] +#CHECK: lctlg %c0, %c0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x2f] +#CHECK: lctlg %c0, %c0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x2f] +#CHECK: lctlg %c0, %c0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x2f] +#CHECK: lctlg %c0, %c0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x2f] +#CHECK: lctlg %c0, %c0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x2f] +#CHECK: lctlg %c0, %c0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x2f] +#CHECK: lctlg %c0, %c0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x2f] + + lctlg %c0,%c0,0 + lctlg %c0,%c15,0 + lctlg %c14,%c15,0 + lctlg %c15,%c15,0 + lctlg %c0,%c0,-524288 + lctlg %c0,%c0,-1 + lctlg %c0,%c0,0 + lctlg %c0,%c0,1 + lctlg %c0,%c0,524287 + lctlg %c0,%c0,0(%r1) + lctlg %c0,%c0,0(%r15) + lctlg %c0,%c0,524287(%r1) + lctlg %c0,%c0,524287(%r15) + #CHECK: lcxbr %f0, %f8 # encoding: [0xb3,0x43,0x00,0x08] #CHECK: lcxbr %f0, %f13 # encoding: [0xb3,0x43,0x00,0x0d] #CHECK: lcxbr %f13, %f0 # encoding: [0xb3,0x43,0x00,0xd0] @@ -9291,6 +9617,20 @@ lnxr %f13,%f0 lnxr %f13,%f9 +#CHECK: lpctl 0 # encoding: [0xb2,0x85,0x00,0x00] +#CHECK: lpctl 0(%r1) # encoding: [0xb2,0x85,0x10,0x00] +#CHECK: lpctl 0(%r15) # encoding: [0xb2,0x85,0xf0,0x00] +#CHECK: lpctl 4095 # encoding: [0xb2,0x85,0x0f,0xff] +#CHECK: lpctl 4095(%r1) # encoding: [0xb2,0x85,0x1f,0xff] +#CHECK: lpctl 4095(%r15) # encoding: [0xb2,0x85,0xff,0xff] + + lpctl 0 + lpctl 0(%r1) + lpctl 0(%r15) + lpctl 4095 + lpctl 4095(%r1) + lpctl 4095(%r15) + #CHECK: lpdbr %f0, %f9 # encoding: [0xb3,0x10,0x00,0x09] #CHECK: lpdbr %f0, %f15 # encoding: [0xb3,0x10,0x00,0x0f] #CHECK: lpdbr %f15, %f0 # encoding: [0xb3,0x10,0x00,0xf0] @@ -9351,6 +9691,20 @@ lpgr %r15,%r0 lpgr %r7,%r8 +#CHECK: lpp 0 # encoding: [0xb2,0x80,0x00,0x00] +#CHECK: lpp 0(%r1) # encoding: [0xb2,0x80,0x10,0x00] +#CHECK: lpp 0(%r15) # encoding: [0xb2,0x80,0xf0,0x00] +#CHECK: lpp 4095 # encoding: [0xb2,0x80,0x0f,0xff] +#CHECK: lpp 4095(%r1) # encoding: [0xb2,0x80,0x1f,0xff] +#CHECK: lpp 4095(%r15) # encoding: [0xb2,0x80,0xff,0xff] + + lpp 0 + lpp 0(%r1) + lpp 0(%r15) + lpp 4095 + lpp 4095(%r1) + lpp 4095(%r15) + #CHECK: lpq %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x8f] #CHECK: lpq %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x8f] #CHECK: lpq %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x8f] @@ -9383,6 +9737,48 @@ lpr %r15,%r0 lpr %r7,%r8 +#CHECK: lpsw 0 # encoding: [0x82,0x00,0x00,0x00] +#CHECK: lpsw 0(%r1) # encoding: [0x82,0x00,0x10,0x00] +#CHECK: lpsw 0(%r15) # encoding: [0x82,0x00,0xf0,0x00] +#CHECK: lpsw 4095 # encoding: [0x82,0x00,0x0f,0xff] +#CHECK: lpsw 4095(%r1) # encoding: [0x82,0x00,0x1f,0xff] +#CHECK: lpsw 4095(%r15) # encoding: [0x82,0x00,0xff,0xff] + + lpsw 0 + lpsw 0(%r1) + lpsw 0(%r15) + lpsw 4095 + lpsw 4095(%r1) + lpsw 4095(%r15) + +#CHECK: lpswe 0 # encoding: [0xb2,0xb2,0x00,0x00] +#CHECK: lpswe 0(%r1) # encoding: [0xb2,0xb2,0x10,0x00] +#CHECK: lpswe 0(%r15) # encoding: [0xb2,0xb2,0xf0,0x00] +#CHECK: lpswe 4095 # encoding: [0xb2,0xb2,0x0f,0xff] +#CHECK: lpswe 4095(%r1) # encoding: [0xb2,0xb2,0x1f,0xff] +#CHECK: lpswe 4095(%r15) # encoding: [0xb2,0xb2,0xff,0xff] + + lpswe 0 + lpswe 0(%r1) + lpswe 0(%r15) + lpswe 4095 + lpswe 4095(%r1) + lpswe 4095(%r15) + +#CHECK: lptea %r0, %r0, %r0, 0 # encoding: [0xb9,0xaa,0x00,0x00] +#CHECK: lptea %r0, %r0, %r0, 15 # encoding: [0xb9,0xaa,0x0f,0x00] +#CHECK: lptea %r0, %r0, %r15, 0 # encoding: [0xb9,0xaa,0x00,0x0f] +#CHECK: lptea %r0, %r15, %r0, 0 # encoding: [0xb9,0xaa,0xf0,0x00] +#CHECK: lptea %r4, %r5, %r6, 7 # encoding: [0xb9,0xaa,0x57,0x46] +#CHECK: lptea %r15, %r0, %r0, 0 # encoding: [0xb9,0xaa,0x00,0xf0] + + lptea %r0, %r0, %r0, 0 + lptea %r0, %r0, %r0, 15 + lptea %r0, %r0, %r15, 0 + lptea %r0, %r15, %r0, 0 + lptea %r4, %r5, %r6, 7 + lptea %r15, %r0, %r0, 0 + #CHECK: lpxbr %f0, %f8 # encoding: [0xb3,0x40,0x00,0x08] #CHECK: lpxbr %f0, %f13 # encoding: [0xb3,0x40,0x00,0x0d] #CHECK: lpxbr %f13, %f0 # encoding: [0xb3,0x40,0x00,0xd0] @@ -9413,6 +9809,66 @@ lr %r15,%r0 lr %r15,%r9 +#CHECK: lra %r0, 0 # encoding: [0xb1,0x00,0x00,0x00] +#CHECK: lra %r0, 4095 # encoding: [0xb1,0x00,0x0f,0xff] +#CHECK: lra %r0, 0(%r1) # encoding: [0xb1,0x00,0x10,0x00] +#CHECK: lra %r0, 0(%r15) # encoding: [0xb1,0x00,0xf0,0x00] +#CHECK: lra %r0, 4095(%r1,%r15) # encoding: [0xb1,0x01,0xff,0xff] +#CHECK: lra %r0, 4095(%r15,%r1) # encoding: [0xb1,0x0f,0x1f,0xff] +#CHECK: lra %r15, 0 # encoding: [0xb1,0xf0,0x00,0x00] + + lra %r0, 0 + lra %r0, 4095 + lra %r0, 0(%r1) + lra %r0, 0(%r15) + lra %r0, 4095(%r1,%r15) + lra %r0, 4095(%r15,%r1) + lra %r15, 0 + +#CHECK: lrag %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x03] +#CHECK: lrag %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x03] +#CHECK: lrag %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x03] +#CHECK: lrag %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x03] +#CHECK: lrag %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x03] +#CHECK: lrag %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x03] +#CHECK: lrag %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x03] +#CHECK: lrag %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x03] +#CHECK: lrag %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x03] +#CHECK: lrag %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x03] + + lrag %r0, -524288 + lrag %r0, -1 + lrag %r0, 0 + lrag %r0, 1 + lrag %r0, 524287 + lrag %r0, 0(%r1) + lrag %r0, 0(%r15) + lrag %r0, 524287(%r1,%r15) + lrag %r0, 524287(%r15,%r1) + lrag %r15, 0 + +#CHECK: lray %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x13] +#CHECK: lray %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x13] +#CHECK: lray %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x13] +#CHECK: lray %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x13] +#CHECK: lray %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x13] +#CHECK: lray %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x13] +#CHECK: lray %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x13] +#CHECK: lray %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x13] +#CHECK: lray %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x13] +#CHECK: lray %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x13] + + lray %r0, -524288 + lray %r0, -1 + lray %r0, 0 + lray %r0, 1 + lray %r0, 524287 + lray %r0, 0(%r1) + lray %r0, 0(%r15) + lray %r0, 524287(%r1,%r15) + lray %r0, 524287(%r15,%r1) + lray %r15, 0 + #CHECK: lrdr %f0, %f0 # encoding: [0x25,0x00] #CHECK: lrdr %f0, %f13 # encoding: [0x25,0x0d] #CHECK: lrdr %f7, %f8 # encoding: [0x25,0x78] @@ -9564,6 +10020,20 @@ lrvr %r7,%r8 lrvr %r15,%r15 +#CHECK: lsctl 0 # encoding: [0xb2,0x87,0x00,0x00] +#CHECK: lsctl 0(%r1) # encoding: [0xb2,0x87,0x10,0x00] +#CHECK: lsctl 0(%r15) # encoding: [0xb2,0x87,0xf0,0x00] +#CHECK: lsctl 4095 # encoding: [0xb2,0x87,0x0f,0xff] +#CHECK: lsctl 4095(%r1) # encoding: [0xb2,0x87,0x1f,0xff] +#CHECK: lsctl 4095(%r15) # encoding: [0xb2,0x87,0xff,0xff] + + lsctl 0 + lsctl 0(%r1) + lsctl 0(%r15) + lsctl 4095 + lsctl 4095(%r1) + lsctl 4095(%r15) + #CHECK: lt %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x12] #CHECK: lt %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x12] #CHECK: lt %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x12] @@ -9740,6 +10210,26 @@ ltxtr %f13,%f0 ltxtr %f13,%f9 +#CHECK: lura %r0, %r0 # encoding: [0xb2,0x4b,0x00,0x00] +#CHECK: lura %r0, %r15 # encoding: [0xb2,0x4b,0x00,0x0f] +#CHECK: lura %r15, %r0 # encoding: [0xb2,0x4b,0x00,0xf0] +#CHECK: lura %r7, %r8 # encoding: [0xb2,0x4b,0x00,0x78] + + lura %r0,%r0 + lura %r0,%r15 + lura %r15,%r0 + lura %r7,%r8 + +#CHECK: lurag %r0, %r0 # encoding: [0xb9,0x05,0x00,0x00] +#CHECK: lurag %r0, %r15 # encoding: [0xb9,0x05,0x00,0x0f] +#CHECK: lurag %r15, %r0 # encoding: [0xb9,0x05,0x00,0xf0] +#CHECK: lurag %r7, %r8 # encoding: [0xb9,0x05,0x00,0x78] + + lurag %r0,%r0 + lurag %r0,%r15 + lurag %r15,%r0 + lurag %r7,%r8 + #CHECK: lxd %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x25] #CHECK: lxd %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x25] #CHECK: lxd %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x25] @@ -10578,6 +11068,20 @@ ms %r0, 4095(%r15,%r1) ms %r15, 0 +#CHECK: msch 0 # encoding: [0xb2,0x32,0x00,0x00] +#CHECK: msch 0(%r1) # encoding: [0xb2,0x32,0x10,0x00] +#CHECK: msch 0(%r15) # encoding: [0xb2,0x32,0xf0,0x00] +#CHECK: msch 4095 # encoding: [0xb2,0x32,0x0f,0xff] +#CHECK: msch 4095(%r1) # encoding: [0xb2,0x32,0x1f,0xff] +#CHECK: msch 4095(%r15) # encoding: [0xb2,0x32,0xff,0xff] + + msch 0 + msch 0(%r1) + msch 0(%r15) + msch 4095 + msch 4095(%r1) + msch 4095(%r15) + #CHECK: msd %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x3f] #CHECK: msd %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x3f] #CHECK: msd %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x3f] @@ -10816,6 +11320,14 @@ msr %r15,%r0 msr %r7,%r8 +#CHECK: msta %r0 # encoding: [0xb2,0x47,0x00,0x00] +#CHECK: msta %r2 # encoding: [0xb2,0x47,0x00,0x20] +#CHECK: msta %r14 # encoding: [0xb2,0x47,0x00,0xe0] + + msta %r0 + msta %r2 + msta %r14 + #CHECK: msy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x51] #CHECK: msy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x51] #CHECK: msy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x51] @@ -10864,6 +11376,28 @@ mvc 0(256,%r1), 0 mvc 0(256,%r15), 0 +#CHECK: mvcdk 0, 0 # encoding: [0xe5,0x0f,0x00,0x00,0x00,0x00] +#CHECK: mvcdk 0(%r1), 0(%r2) # encoding: [0xe5,0x0f,0x10,0x00,0x20,0x00] +#CHECK: mvcdk 160(%r1), 320(%r15) # encoding: [0xe5,0x0f,0x10,0xa0,0xf1,0x40] +#CHECK: mvcdk 0(%r1), 4095 # encoding: [0xe5,0x0f,0x10,0x00,0x0f,0xff] +#CHECK: mvcdk 0(%r1), 4095(%r2) # encoding: [0xe5,0x0f,0x10,0x00,0x2f,0xff] +#CHECK: mvcdk 0(%r1), 4095(%r15) # encoding: [0xe5,0x0f,0x10,0x00,0xff,0xff] +#CHECK: mvcdk 0(%r1), 0 # encoding: [0xe5,0x0f,0x10,0x00,0x00,0x00] +#CHECK: mvcdk 0(%r15), 0 # encoding: [0xe5,0x0f,0xf0,0x00,0x00,0x00] +#CHECK: mvcdk 4095(%r1), 0 # encoding: [0xe5,0x0f,0x1f,0xff,0x00,0x00] +#CHECK: mvcdk 4095(%r15), 0 # encoding: [0xe5,0x0f,0xff,0xff,0x00,0x00] + + mvcdk 0, 0 + mvcdk 0(%r1), 0(%r2) + mvcdk 160(%r1), 320(%r15) + mvcdk 0(%r1), 4095 + mvcdk 0(%r1), 4095(%r2) + mvcdk 0(%r1), 4095(%r15) + mvcdk 0(%r1), 0 + mvcdk 0(%r15), 0 + mvcdk 4095(%r1), 0 + mvcdk 4095(%r15), 0 + #CHECK: mvcin 0(1), 0 # encoding: [0xe8,0x00,0x00,0x00,0x00,0x00] #CHECK: mvcin 0(1), 0(%r1) # encoding: [0xe8,0x00,0x00,0x00,0x10,0x00] #CHECK: mvcin 0(1), 0(%r15) # encoding: [0xe8,0x00,0x00,0x00,0xf0,0x00] @@ -10966,6 +11500,98 @@ mvclu %r0, %r0, 524287(%r1) mvclu %r14, %r0, 0 +#CHECK: mvcos 0, 0, %r0 # encoding: [0xc8,0x00,0x00,0x00,0x00,0x00] +#CHECK: mvcos 0(%r1), 0(%r15), %r2 # encoding: [0xc8,0x20,0x10,0x00,0xf0,0x00] +#CHECK: mvcos 1(%r1), 0(%r15), %r2 # encoding: [0xc8,0x20,0x10,0x01,0xf0,0x00] +#CHECK: mvcos 4095(%r1), 0(%r15), %r2 # encoding: [0xc8,0x20,0x1f,0xff,0xf0,0x00] +#CHECK: mvcos 0(%r1), 1(%r15), %r2 # encoding: [0xc8,0x20,0x10,0x00,0xf0,0x01] +#CHECK: mvcos 0(%r1), 4095(%r15), %r2 # encoding: [0xc8,0x20,0x10,0x00,0xff,0xff] + + mvcos 0, 0, %r0 + mvcos 0(%r1), 0(%r15), %r2 + mvcos 1(%r1), 0(%r15), %r2 + mvcos 4095(%r1), 0(%r15), %r2 + mvcos 0(%r1), 1(%r15), %r2 + mvcos 0(%r1), 4095(%r15), %r2 + +#CHECK: mvcp 0(%r0), 0, %r3 # encoding: [0xda,0x03,0x00,0x00,0x00,0x00] +#CHECK: mvcp 0(%r1), 0, %r3 # encoding: [0xda,0x13,0x00,0x00,0x00,0x00] +#CHECK: mvcp 0(%r1), 0(%r1), %r3 # encoding: [0xda,0x13,0x00,0x00,0x10,0x00] +#CHECK: mvcp 0(%r1), 0(%r15), %r3 # encoding: [0xda,0x13,0x00,0x00,0xf0,0x00] +#CHECK: mvcp 0(%r1), 4095, %r3 # encoding: [0xda,0x13,0x00,0x00,0x0f,0xff] +#CHECK: mvcp 0(%r1), 4095(%r1), %r3 # encoding: [0xda,0x13,0x00,0x00,0x1f,0xff] +#CHECK: mvcp 0(%r1), 4095(%r15), %r3 # encoding: [0xda,0x13,0x00,0x00,0xff,0xff] +#CHECK: mvcp 0(%r2,%r1), 0, %r3 # encoding: [0xda,0x23,0x10,0x00,0x00,0x00] +#CHECK: mvcp 0(%r2,%r15), 0, %r3 # encoding: [0xda,0x23,0xf0,0x00,0x00,0x00] +#CHECK: mvcp 4095(%r2,%r1), 0, %r3 # encoding: [0xda,0x23,0x1f,0xff,0x00,0x00] +#CHECK: mvcp 4095(%r2,%r15), 0, %r3 # encoding: [0xda,0x23,0xff,0xff,0x00,0x00] +#CHECK: mvcp 0(%r2,%r1), 0, %r3 # encoding: [0xda,0x23,0x10,0x00,0x00,0x00] +#CHECK: mvcp 0(%r2,%r15), 0, %r3 # encoding: [0xda,0x23,0xf0,0x00,0x00,0x00] + + mvcp 0(%r0), 0, %r3 + mvcp 0(%r1), 0, %r3 + mvcp 0(%r1), 0(%r1), %r3 + mvcp 0(%r1), 0(%r15), %r3 + mvcp 0(%r1), 4095, %r3 + mvcp 0(%r1), 4095(%r1), %r3 + mvcp 0(%r1), 4095(%r15), %r3 + mvcp 0(%r2,%r1), 0, %r3 + mvcp 0(%r2,%r15), 0, %r3 + mvcp 4095(%r2,%r1), 0, %r3 + mvcp 4095(%r2,%r15), 0, %r3 + mvcp 0(%r2,%r1), 0, %r3 + mvcp 0(%r2,%r15), 0, %r3 + +#CHECK: mvcs 0(%r0), 0, %r3 # encoding: [0xdb,0x03,0x00,0x00,0x00,0x00] +#CHECK: mvcs 0(%r1), 0, %r3 # encoding: [0xdb,0x13,0x00,0x00,0x00,0x00] +#CHECK: mvcs 0(%r1), 0(%r1), %r3 # encoding: [0xdb,0x13,0x00,0x00,0x10,0x00] +#CHECK: mvcs 0(%r1), 0(%r15), %r3 # encoding: [0xdb,0x13,0x00,0x00,0xf0,0x00] +#CHECK: mvcs 0(%r1), 4095, %r3 # encoding: [0xdb,0x13,0x00,0x00,0x0f,0xff] +#CHECK: mvcs 0(%r1), 4095(%r1), %r3 # encoding: [0xdb,0x13,0x00,0x00,0x1f,0xff] +#CHECK: mvcs 0(%r1), 4095(%r15), %r3 # encoding: [0xdb,0x13,0x00,0x00,0xff,0xff] +#CHECK: mvcs 0(%r2,%r1), 0, %r3 # encoding: [0xdb,0x23,0x10,0x00,0x00,0x00] +#CHECK: mvcs 0(%r2,%r15), 0, %r3 # encoding: [0xdb,0x23,0xf0,0x00,0x00,0x00] +#CHECK: mvcs 4095(%r2,%r1), 0, %r3 # encoding: [0xdb,0x23,0x1f,0xff,0x00,0x00] +#CHECK: mvcs 4095(%r2,%r15), 0, %r3 # encoding: [0xdb,0x23,0xff,0xff,0x00,0x00] +#CHECK: mvcs 0(%r2,%r1), 0, %r3 # encoding: [0xdb,0x23,0x10,0x00,0x00,0x00] +#CHECK: mvcs 0(%r2,%r15), 0, %r3 # encoding: [0xdb,0x23,0xf0,0x00,0x00,0x00] + + mvcs 0(%r0), 0, %r3 + mvcs 0(%r1), 0, %r3 + mvcs 0(%r1), 0(%r1), %r3 + mvcs 0(%r1), 0(%r15), %r3 + mvcs 0(%r1), 4095, %r3 + mvcs 0(%r1), 4095(%r1), %r3 + mvcs 0(%r1), 4095(%r15), %r3 + mvcs 0(%r2,%r1), 0, %r3 + mvcs 0(%r2,%r15), 0, %r3 + mvcs 4095(%r2,%r1), 0, %r3 + mvcs 4095(%r2,%r15), 0, %r3 + mvcs 0(%r2,%r1), 0, %r3 + mvcs 0(%r2,%r15), 0, %r3 + +#CHECK: mvcsk 0, 0 # encoding: [0xe5,0x0e,0x00,0x00,0x00,0x00] +#CHECK: mvcsk 0(%r1), 0(%r2) # encoding: [0xe5,0x0e,0x10,0x00,0x20,0x00] +#CHECK: mvcsk 160(%r1), 320(%r15) # encoding: [0xe5,0x0e,0x10,0xa0,0xf1,0x40] +#CHECK: mvcsk 0(%r1), 4095 # encoding: [0xe5,0x0e,0x10,0x00,0x0f,0xff] +#CHECK: mvcsk 0(%r1), 4095(%r2) # encoding: [0xe5,0x0e,0x10,0x00,0x2f,0xff] +#CHECK: mvcsk 0(%r1), 4095(%r15) # encoding: [0xe5,0x0e,0x10,0x00,0xff,0xff] +#CHECK: mvcsk 0(%r1), 0 # encoding: [0xe5,0x0e,0x10,0x00,0x00,0x00] +#CHECK: mvcsk 0(%r15), 0 # encoding: [0xe5,0x0e,0xf0,0x00,0x00,0x00] +#CHECK: mvcsk 4095(%r1), 0 # encoding: [0xe5,0x0e,0x1f,0xff,0x00,0x00] +#CHECK: mvcsk 4095(%r15), 0 # encoding: [0xe5,0x0e,0xff,0xff,0x00,0x00] + + mvcsk 0, 0 + mvcsk 0(%r1), 0(%r2) + mvcsk 160(%r1), 320(%r15) + mvcsk 0(%r1), 4095 + mvcsk 0(%r1), 4095(%r2) + mvcsk 0(%r1), 4095(%r15) + mvcsk 0(%r1), 0 + mvcsk 0(%r15), 0 + mvcsk 4095(%r1), 0 + mvcsk 4095(%r15), 0 + #CHECK: mvghi 0, 0 # encoding: [0xe5,0x48,0x00,0x00,0x00,0x00] #CHECK: mvghi 4095, 0 # encoding: [0xe5,0x48,0x0f,0xff,0x00,0x00] #CHECK: mvghi 0, -32768 # encoding: [0xe5,0x48,0x00,0x00,0x80,0x00] @@ -11132,6 +11758,16 @@ mvo 0(1), 0(16,%r1) mvo 0(1), 0(16,%r15) +#CHECK: mvpg %r0, %r0 # encoding: [0xb2,0x54,0x00,0x00] +#CHECK: mvpg %r0, %r15 # encoding: [0xb2,0x54,0x00,0x0f] +#CHECK: mvpg %r15, %r0 # encoding: [0xb2,0x54,0x00,0xf0] +#CHECK: mvpg %r7, %r8 # encoding: [0xb2,0x54,0x00,0x78] + + mvpg %r0,%r0 + mvpg %r0,%r15 + mvpg %r15,%r0 + mvpg %r7,%r8 + #CHECK: mvst %r0, %r0 # encoding: [0xb2,0x55,0x00,0x00] #CHECK: mvst %r0, %r15 # encoding: [0xb2,0x55,0x00,0x0f] #CHECK: mvst %r15, %r0 # encoding: [0xb2,0x55,0x00,0xf0] @@ -11790,6 +12426,24 @@ pack 0(1), 0(16,%r1) pack 0(1), 0(16,%r15) +#CHECK: palb # encoding: [0xb2,0x48,0x00,0x00] + + palb + +#CHECK: pc 0 # encoding: [0xb2,0x18,0x00,0x00] +#CHECK: pc 0(%r1) # encoding: [0xb2,0x18,0x10,0x00] +#CHECK: pc 0(%r15) # encoding: [0xb2,0x18,0xf0,0x00] +#CHECK: pc 4095 # encoding: [0xb2,0x18,0x0f,0xff] +#CHECK: pc 4095(%r1) # encoding: [0xb2,0x18,0x1f,0xff] +#CHECK: pc 4095(%r15) # encoding: [0xb2,0x18,0xff,0xff] + + pc 0 + pc 0(%r1) + pc 0(%r15) + pc 4095 + pc 4095(%r1) + pc 4095(%r15) + #CHECK: pfd 0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x36] #CHECK: pfd 0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x36] #CHECK: pfd 0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x36] @@ -11849,9 +12503,45 @@ pfdrl 7, frob@PLT pfdrl 8, frob@PLT +#CHECK: pfmf %r0, %r0 # encoding: [0xb9,0xaf,0x00,0x00] +#CHECK: pfmf %r0, %r15 # encoding: [0xb9,0xaf,0x00,0x0f] +#CHECK: pfmf %r15, %r0 # encoding: [0xb9,0xaf,0x00,0xf0] +#CHECK: pfmf %r7, %r8 # encoding: [0xb9,0xaf,0x00,0x78] +#CHECK: pfmf %r15, %r15 # encoding: [0xb9,0xaf,0x00,0xff] + + pfmf %r0,%r0 + pfmf %r0,%r15 + pfmf %r15,%r0 + pfmf %r7,%r8 + pfmf %r15,%r15 + #CHECK: pfpo # encoding: [0x01,0x0a] pfpo +#CHECK: pgin %r0, %r0 # encoding: [0xb2,0x2e,0x00,0x00] +#CHECK: pgin %r0, %r15 # encoding: [0xb2,0x2e,0x00,0x0f] +#CHECK: pgin %r15, %r0 # encoding: [0xb2,0x2e,0x00,0xf0] +#CHECK: pgin %r7, %r8 # encoding: [0xb2,0x2e,0x00,0x78] +#CHECK: pgin %r15, %r15 # encoding: [0xb2,0x2e,0x00,0xff] + + pgin %r0,%r0 + pgin %r0,%r15 + pgin %r15,%r0 + pgin %r7,%r8 + pgin %r15,%r15 + +#CHECK: pgout %r0, %r0 # encoding: [0xb2,0x2f,0x00,0x00] +#CHECK: pgout %r0, %r15 # encoding: [0xb2,0x2f,0x00,0x0f] +#CHECK: pgout %r15, %r0 # encoding: [0xb2,0x2f,0x00,0xf0] +#CHECK: pgout %r7, %r8 # encoding: [0xb2,0x2f,0x00,0x78] +#CHECK: pgout %r15, %r15 # encoding: [0xb2,0x2f,0x00,0xff] + + pgout %r0,%r0 + pgout %r0,%r15 + pgout %r15,%r0 + pgout %r7,%r8 + pgout %r15,%r15 + #CHECK: pka 0, 0(1) # encoding: [0xe9,0x00,0x00,0x00,0x00,0x00] #CHECK: pka 0, 0(1,%r1) # encoding: [0xe9,0x00,0x00,0x00,0x10,0x00] #CHECK: pka 0, 0(1,%r15) # encoding: [0xe9,0x00,0x00,0x00,0xf0,0x00] @@ -11919,8 +12609,45 @@ plo %r2, 0(%r1), %r4, 4095(%r15) #CHECK: pr # encoding: [0x01,0x01] + pr +#CHECK: pt %r0, %r0 # encoding: [0xb2,0x28,0x00,0x00] +#CHECK: pt %r0, %r15 # encoding: [0xb2,0x28,0x00,0x0f] +#CHECK: pt %r15, %r0 # encoding: [0xb2,0x28,0x00,0xf0] +#CHECK: pt %r7, %r8 # encoding: [0xb2,0x28,0x00,0x78] + + pt %r0,%r0 + pt %r0,%r15 + pt %r15,%r0 + pt %r7,%r8 + +#CHECK: ptf %r0 # encoding: [0xb9,0xa2,0x00,0x00] +#CHECK: ptf %r1 # encoding: [0xb9,0xa2,0x00,0x10] +#CHECK: ptf %r15 # encoding: [0xb9,0xa2,0x00,0xf0] + + ptf %r0 + ptf %r1 + ptf %r15 + +#CHECK: ptff # encoding: [0x01,0x04] + + ptff + +#CHECK: pti %r0, %r0 # encoding: [0xb9,0x9e,0x00,0x00] +#CHECK: pti %r0, %r15 # encoding: [0xb9,0x9e,0x00,0x0f] +#CHECK: pti %r15, %r0 # encoding: [0xb9,0x9e,0x00,0xf0] +#CHECK: pti %r7, %r8 # encoding: [0xb9,0x9e,0x00,0x78] + + pti %r0,%r0 + pti %r0,%r15 + pti %r15,%r0 + pti %r7,%r8 + +#CHECK: ptlb # encoding: [0xb2,0x0d,0x00,0x00] + + ptlb + #CHECK: qadtr %f0, %f0, %f0, 0 # encoding: [0xb3,0xf5,0x00,0x00] #CHECK: qadtr %f0, %f0, %f0, 15 # encoding: [0xb3,0xf5,0x0f,0x00] #CHECK: qadtr %f0, %f0, %f15, 0 # encoding: [0xb3,0xf5,0x00,0x0f] @@ -11949,6 +12676,38 @@ qaxtr %f8, %f8, %f8, 8 qaxtr %f13, %f0, %f0, 0 +#CHECK: qctri 0 # encoding: [0xb2,0x8e,0x00,0x00] +#CHECK: qctri 0(%r1) # encoding: [0xb2,0x8e,0x10,0x00] +#CHECK: qctri 0(%r15) # encoding: [0xb2,0x8e,0xf0,0x00] +#CHECK: qctri 4095 # encoding: [0xb2,0x8e,0x0f,0xff] +#CHECK: qctri 4095(%r1) # encoding: [0xb2,0x8e,0x1f,0xff] +#CHECK: qctri 4095(%r15) # encoding: [0xb2,0x8e,0xff,0xff] + + qctri 0 + qctri 0(%r1) + qctri 0(%r15) + qctri 4095 + qctri 4095(%r1) + qctri 4095(%r15) + +#CHECK: qsi 0 # encoding: [0xb2,0x86,0x00,0x00] +#CHECK: qsi 0(%r1) # encoding: [0xb2,0x86,0x10,0x00] +#CHECK: qsi 0(%r15) # encoding: [0xb2,0x86,0xf0,0x00] +#CHECK: qsi 4095 # encoding: [0xb2,0x86,0x0f,0xff] +#CHECK: qsi 4095(%r1) # encoding: [0xb2,0x86,0x1f,0xff] +#CHECK: qsi 4095(%r15) # encoding: [0xb2,0x86,0xff,0xff] + + qsi 0 + qsi 0(%r1) + qsi 0(%r15) + qsi 4095 + qsi 4095(%r1) + qsi 4095(%r15) + +#CHECK: rchp # encoding: [0xb2,0x3b,0x00,0x00] + + rchp + #CHECK: risbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x55] #CHECK: risbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55] #CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55] @@ -12049,6 +12808,32 @@ rosbg %r15,%r0,0,0,0 rosbg %r4,%r5,6,7,8 +#CHECK: rp 0 # encoding: [0xb2,0x77,0x00,0x00] +#CHECK: rp 0(%r1) # encoding: [0xb2,0x77,0x10,0x00] +#CHECK: rp 0(%r15) # encoding: [0xb2,0x77,0xf0,0x00] +#CHECK: rp 4095 # encoding: [0xb2,0x77,0x0f,0xff] +#CHECK: rp 4095(%r1) # encoding: [0xb2,0x77,0x1f,0xff] +#CHECK: rp 4095(%r15) # encoding: [0xb2,0x77,0xff,0xff] + + rp 0 + rp 0(%r1) + rp 0(%r15) + rp 4095 + rp 4095(%r1) + rp 4095(%r15) + +#CHECK: rrbe %r0, %r0 # encoding: [0xb2,0x2a,0x00,0x00] +#CHECK: rrbe %r0, %r15 # encoding: [0xb2,0x2a,0x00,0x0f] +#CHECK: rrbe %r15, %r0 # encoding: [0xb2,0x2a,0x00,0xf0] +#CHECK: rrbe %r7, %r8 # encoding: [0xb2,0x2a,0x00,0x78] +#CHECK: rrbe %r15, %r15 # encoding: [0xb2,0x2a,0x00,0xff] + + rrbe %r0,%r0 + rrbe %r0,%r15 + rrbe %r15,%r0 + rrbe %r7,%r8 + rrbe %r15,%r15 + #CHECK: rrdtr %f0, %f0, %f0, 0 # encoding: [0xb3,0xf7,0x00,0x00] #CHECK: rrdtr %f0, %f0, %f0, 15 # encoding: [0xb3,0xf7,0x0f,0x00] #CHECK: rrdtr %f0, %f0, %f15, 0 # encoding: [0xb3,0xf7,0x00,0x0f] @@ -12077,6 +12862,10 @@ rrxtr %f8, %f8, %f8, 8 rrxtr %f13, %f0, %f0, 0 +#CHECK: rsch # encoding: [0xb2,0x38,0x00,0x00] + + rsch + #CHECK: rxsbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x57] #CHECK: rxsbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x57] #CHECK: rxsbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x57] @@ -12109,6 +12898,38 @@ s %r0, 4095(%r15,%r1) s %r15, 0 +#CHECK: sac 0 # encoding: [0xb2,0x19,0x00,0x00] +#CHECK: sac 0(%r1) # encoding: [0xb2,0x19,0x10,0x00] +#CHECK: sac 0(%r15) # encoding: [0xb2,0x19,0xf0,0x00] +#CHECK: sac 4095 # encoding: [0xb2,0x19,0x0f,0xff] +#CHECK: sac 4095(%r1) # encoding: [0xb2,0x19,0x1f,0xff] +#CHECK: sac 4095(%r15) # encoding: [0xb2,0x19,0xff,0xff] + + sac 0 + sac 0(%r1) + sac 0(%r15) + sac 4095 + sac 4095(%r1) + sac 4095(%r15) + +#CHECK: sacf 0 # encoding: [0xb2,0x79,0x00,0x00] +#CHECK: sacf 0(%r1) # encoding: [0xb2,0x79,0x10,0x00] +#CHECK: sacf 0(%r15) # encoding: [0xb2,0x79,0xf0,0x00] +#CHECK: sacf 4095 # encoding: [0xb2,0x79,0x0f,0xff] +#CHECK: sacf 4095(%r1) # encoding: [0xb2,0x79,0x1f,0xff] +#CHECK: sacf 4095(%r15) # encoding: [0xb2,0x79,0xff,0xff] + + sacf 0 + sacf 0(%r1) + sacf 0(%r15) + sacf 4095 + sacf 4095(%r1) + sacf 4095(%r15) + +#CHECK: sal # encoding: [0xb2,0x37,0x00,0x00] + + sal + #CHECK: sam24 # encoding: [0x01,0x0c] #CHECK: sam31 # encoding: [0x01,0x0d] #CHECK: sam64 # encoding: [0x01,0x0e] @@ -12129,6 +12950,52 @@ sar %a7, %r8 sar %a15, %r15 +#CHECK: scctr %r0, %r0 # encoding: [0xb2,0xe0,0x00,0x00] +#CHECK: scctr %r0, %r15 # encoding: [0xb2,0xe0,0x00,0x0f] +#CHECK: scctr %r15, %r0 # encoding: [0xb2,0xe0,0x00,0xf0] +#CHECK: scctr %r7, %r8 # encoding: [0xb2,0xe0,0x00,0x78] + + scctr %r0,%r0 + scctr %r0,%r15 + scctr %r15,%r0 + scctr %r7,%r8 + +#CHECK: schm # encoding: [0xb2,0x3c,0x00,0x00] + + schm + +#CHECK: sck 0 # encoding: [0xb2,0x04,0x00,0x00] +#CHECK: sck 0(%r1) # encoding: [0xb2,0x04,0x10,0x00] +#CHECK: sck 0(%r15) # encoding: [0xb2,0x04,0xf0,0x00] +#CHECK: sck 4095 # encoding: [0xb2,0x04,0x0f,0xff] +#CHECK: sck 4095(%r1) # encoding: [0xb2,0x04,0x1f,0xff] +#CHECK: sck 4095(%r15) # encoding: [0xb2,0x04,0xff,0xff] + + sck 0 + sck 0(%r1) + sck 0(%r15) + sck 4095 + sck 4095(%r1) + sck 4095(%r15) + +#CHECK: sckc 0 # encoding: [0xb2,0x06,0x00,0x00] +#CHECK: sckc 0(%r1) # encoding: [0xb2,0x06,0x10,0x00] +#CHECK: sckc 0(%r15) # encoding: [0xb2,0x06,0xf0,0x00] +#CHECK: sckc 4095 # encoding: [0xb2,0x06,0x0f,0xff] +#CHECK: sckc 4095(%r1) # encoding: [0xb2,0x06,0x1f,0xff] +#CHECK: sckc 4095(%r15) # encoding: [0xb2,0x06,0xff,0xff] + + sckc 0 + sckc 0(%r1) + sckc 0(%r15) + sckc 4095 + sckc 4095(%r1) + sckc 4095(%r15) + +#CHECK: sckpf # encoding: [0x01,0x07] + + sckpf + #CHECK: sd %f0, 0 # encoding: [0x6b,0x00,0x00,0x00] #CHECK: sd %f0, 4095 # encoding: [0x6b,0x00,0x0f,0xff] #CHECK: sd %f0, 0(%r1) # encoding: [0x6b,0x00,0x10,0x00] @@ -12363,6 +13230,56 @@ shy %r0, 524287(%r15,%r1) shy %r15, 0 +#CHECK: sie 0 # encoding: [0xb2,0x14,0x00,0x00] +#CHECK: sie 0(%r1) # encoding: [0xb2,0x14,0x10,0x00] +#CHECK: sie 0(%r15) # encoding: [0xb2,0x14,0xf0,0x00] +#CHECK: sie 4095 # encoding: [0xb2,0x14,0x0f,0xff] +#CHECK: sie 4095(%r1) # encoding: [0xb2,0x14,0x1f,0xff] +#CHECK: sie 4095(%r15) # encoding: [0xb2,0x14,0xff,0xff] + + sie 0 + sie 0(%r1) + sie 0(%r15) + sie 4095 + sie 4095(%r1) + sie 4095(%r15) + +#CHECK: siga 0 # encoding: [0xb2,0x74,0x00,0x00] +#CHECK: siga 0(%r1) # encoding: [0xb2,0x74,0x10,0x00] +#CHECK: siga 0(%r15) # encoding: [0xb2,0x74,0xf0,0x00] +#CHECK: siga 4095 # encoding: [0xb2,0x74,0x0f,0xff] +#CHECK: siga 4095(%r1) # encoding: [0xb2,0x74,0x1f,0xff] +#CHECK: siga 4095(%r15) # encoding: [0xb2,0x74,0xff,0xff] + + siga 0 + siga 0(%r1) + siga 0(%r15) + siga 4095 + siga 4095(%r1) + siga 4095(%r15) + +#CHECK: sigp %r0, %r0, 0 # encoding: [0xae,0x00,0x00,0x00] +#CHECK: sigp %r0, %r15, 0 # encoding: [0xae,0x0f,0x00,0x00] +#CHECK: sigp %r14, %r15, 0 # encoding: [0xae,0xef,0x00,0x00] +#CHECK: sigp %r15, %r15, 0 # encoding: [0xae,0xff,0x00,0x00] +#CHECK: sigp %r0, %r0, 4095 # encoding: [0xae,0x00,0x0f,0xff] +#CHECK: sigp %r0, %r0, 1 # encoding: [0xae,0x00,0x00,0x01] +#CHECK: sigp %r0, %r0, 0(%r1) # encoding: [0xae,0x00,0x10,0x00] +#CHECK: sigp %r0, %r0, 0(%r15) # encoding: [0xae,0x00,0xf0,0x00] +#CHECK: sigp %r0, %r0, 4095(%r1) # encoding: [0xae,0x00,0x1f,0xff] +#CHECK: sigp %r0, %r0, 4095(%r15) # encoding: [0xae,0x00,0xff,0xff] + + sigp %r0,%r0,0 + sigp %r0,%r15,0 + sigp %r14,%r15,0 + sigp %r15,%r15,0 + sigp %r0,%r0,4095 + sigp %r0,%r0,1 + sigp %r0,%r0,0(%r1) + sigp %r0,%r0,0(%r15) + sigp %r0,%r0,4095(%r1) + sigp %r0,%r0,4095(%r15) + #CHECK: sl %r0, 0 # encoding: [0x5f,0x00,0x00,0x00] #CHECK: sl %r0, 4095 # encoding: [0x5f,0x00,0x0f,0xff] #CHECK: sl %r0, 0(%r1) # encoding: [0x5f,0x00,0x10,0x00] @@ -12749,6 +13666,30 @@ sp 0(1), 0(16,%r1) sp 0(1), 0(16,%r15) +#CHECK: spctr %r0, %r0 # encoding: [0xb2,0xe1,0x00,0x00] +#CHECK: spctr %r0, %r15 # encoding: [0xb2,0xe1,0x00,0x0f] +#CHECK: spctr %r15, %r0 # encoding: [0xb2,0xe1,0x00,0xf0] +#CHECK: spctr %r7, %r8 # encoding: [0xb2,0xe1,0x00,0x78] + + spctr %r0,%r0 + spctr %r0,%r15 + spctr %r15,%r0 + spctr %r7,%r8 + +#CHECK: spka 0 # encoding: [0xb2,0x0a,0x00,0x00] +#CHECK: spka 0(%r1) # encoding: [0xb2,0x0a,0x10,0x00] +#CHECK: spka 0(%r15) # encoding: [0xb2,0x0a,0xf0,0x00] +#CHECK: spka 4095 # encoding: [0xb2,0x0a,0x0f,0xff] +#CHECK: spka 4095(%r1) # encoding: [0xb2,0x0a,0x1f,0xff] +#CHECK: spka 4095(%r15) # encoding: [0xb2,0x0a,0xff,0xff] + + spka 0 + spka 0(%r1) + spka 0(%r15) + spka 4095 + spka 4095(%r1) + spka 4095(%r15) + #CHECK: spm %r0 # encoding: [0x04,0x00] #CHECK: spm %r1 # encoding: [0x04,0x10] #CHECK: spm %r15 # encoding: [0x04,0xf0] @@ -12757,6 +13698,34 @@ spm %r1 spm %r15 +#CHECK: spt 0 # encoding: [0xb2,0x08,0x00,0x00] +#CHECK: spt 0(%r1) # encoding: [0xb2,0x08,0x10,0x00] +#CHECK: spt 0(%r15) # encoding: [0xb2,0x08,0xf0,0x00] +#CHECK: spt 4095 # encoding: [0xb2,0x08,0x0f,0xff] +#CHECK: spt 4095(%r1) # encoding: [0xb2,0x08,0x1f,0xff] +#CHECK: spt 4095(%r15) # encoding: [0xb2,0x08,0xff,0xff] + + spt 0 + spt 0(%r1) + spt 0(%r15) + spt 4095 + spt 4095(%r1) + spt 4095(%r15) + +#CHECK: spx 0 # encoding: [0xb2,0x10,0x00,0x00] +#CHECK: spx 0(%r1) # encoding: [0xb2,0x10,0x10,0x00] +#CHECK: spx 0(%r15) # encoding: [0xb2,0x10,0xf0,0x00] +#CHECK: spx 4095 # encoding: [0xb2,0x10,0x0f,0xff] +#CHECK: spx 4095(%r1) # encoding: [0xb2,0x10,0x1f,0xff] +#CHECK: spx 4095(%r15) # encoding: [0xb2,0x10,0xff,0xff] + + spx 0 + spx 0(%r1) + spx 0(%r15) + spx 4095 + spx 4095(%r1) + spx 4095(%r15) + #CHECK: sqd %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x35] #CHECK: sqd %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x35] #CHECK: sqd %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x35] @@ -13131,6 +14100,62 @@ srxt %f13, %f0, 0 srxt %f13, %f13, 0 +#CHECK: ssar %r0 # encoding: [0xb2,0x25,0x00,0x00] +#CHECK: ssar %r1 # encoding: [0xb2,0x25,0x00,0x10] +#CHECK: ssar %r15 # encoding: [0xb2,0x25,0x00,0xf0] + + ssar %r0 + ssar %r1 + ssar %r15 + +#CHECK: ssair %r0 # encoding: [0xb9,0x9f,0x00,0x00] +#CHECK: ssair %r1 # encoding: [0xb9,0x9f,0x00,0x10] +#CHECK: ssair %r15 # encoding: [0xb9,0x9f,0x00,0xf0] + + ssair %r0 + ssair %r1 + ssair %r15 + +#CHECK: ssch 0 # encoding: [0xb2,0x33,0x00,0x00] +#CHECK: ssch 0(%r1) # encoding: [0xb2,0x33,0x10,0x00] +#CHECK: ssch 0(%r15) # encoding: [0xb2,0x33,0xf0,0x00] +#CHECK: ssch 4095 # encoding: [0xb2,0x33,0x0f,0xff] +#CHECK: ssch 4095(%r1) # encoding: [0xb2,0x33,0x1f,0xff] +#CHECK: ssch 4095(%r15) # encoding: [0xb2,0x33,0xff,0xff] + + ssch 0 + ssch 0(%r1) + ssch 0(%r15) + ssch 4095 + ssch 4095(%r1) + ssch 4095(%r15) + +#CHECK: sske %r0, %r0 # encoding: [0xb2,0x2b,0x00,0x00] +#CHECK: sske %r0, %r15 # encoding: [0xb2,0x2b,0x00,0x0f] +#CHECK: sske %r15, %r0 # encoding: [0xb2,0x2b,0x00,0xf0] +#CHECK: sske %r0, %r0, 15 # encoding: [0xb2,0x2b,0xf0,0x00] +#CHECK: sske %r4, %r6, 7 # encoding: [0xb2,0x2b,0x70,0x46] + + sske %r0, %r0 + sske %r0, %r15 + sske %r15, %r0 + sske %r0, %r0, 15 + sske %r4, %r6, 7 + +#CHECK: ssm 0 # encoding: [0x80,0x00,0x00,0x00] +#CHECK: ssm 0(%r1) # encoding: [0x80,0x00,0x10,0x00] +#CHECK: ssm 0(%r15) # encoding: [0x80,0x00,0xf0,0x00] +#CHECK: ssm 4095 # encoding: [0x80,0x00,0x0f,0xff] +#CHECK: ssm 4095(%r1) # encoding: [0x80,0x00,0x1f,0xff] +#CHECK: ssm 4095(%r15) # encoding: [0x80,0x00,0xff,0xff] + + ssm 0 + ssm 0(%r1) + ssm 0(%r15) + ssm 4095 + ssm 4095(%r1) + ssm 4095(%r15) + #CHECK: st %r0, 0 # encoding: [0x50,0x00,0x00,0x00] #CHECK: st %r0, 4095 # encoding: [0x50,0x00,0x0f,0xff] #CHECK: st %r0, 0(%r1) # encoding: [0x50,0x00,0x10,0x00] @@ -13197,6 +14222,20 @@ stamy %a0,%a0,524287(%r1) stamy %a0,%a0,524287(%r15) +#CHECK: stap 0 # encoding: [0xb2,0x12,0x00,0x00] +#CHECK: stap 0(%r1) # encoding: [0xb2,0x12,0x10,0x00] +#CHECK: stap 0(%r15) # encoding: [0xb2,0x12,0xf0,0x00] +#CHECK: stap 4095 # encoding: [0xb2,0x12,0x0f,0xff] +#CHECK: stap 4095(%r1) # encoding: [0xb2,0x12,0x1f,0xff] +#CHECK: stap 4095(%r15) # encoding: [0xb2,0x12,0xff,0xff] + + stap 0 + stap 0(%r1) + stap 0(%r15) + stap 4095 + stap 4095(%r1) + stap 4095(%r15) + #CHECK: stc %r0, 0 # encoding: [0x42,0x00,0x00,0x00] #CHECK: stc %r0, 4095 # encoding: [0x42,0x00,0x0f,0xff] #CHECK: stc %r0, 0(%r1) # encoding: [0x42,0x00,0x10,0x00] @@ -13227,6 +14266,20 @@ stck 4095(%r1) stck 4095(%r15) +#CHECK: stckc 0 # encoding: [0xb2,0x07,0x00,0x00] +#CHECK: stckc 0(%r1) # encoding: [0xb2,0x07,0x10,0x00] +#CHECK: stckc 0(%r15) # encoding: [0xb2,0x07,0xf0,0x00] +#CHECK: stckc 4095 # encoding: [0xb2,0x07,0x0f,0xff] +#CHECK: stckc 4095(%r1) # encoding: [0xb2,0x07,0x1f,0xff] +#CHECK: stckc 4095(%r15) # encoding: [0xb2,0x07,0xff,0xff] + + stckc 0 + stckc 0(%r1) + stckc 0(%r15) + stckc 4095 + stckc 4095(%r1) + stckc 4095(%r15) + #CHECK: stcke 0 # encoding: [0xb2,0x78,0x00,0x00] #CHECK: stcke 0(%r1) # encoding: [0xb2,0x78,0x10,0x00] #CHECK: stcke 0(%r15) # encoding: [0xb2,0x78,0xf0,0x00] @@ -13315,6 +14368,84 @@ stcmy %r0, 0, 524287(%r1) stcmy %r15, 0, 0 +#CHECK: stcps 0 # encoding: [0xb2,0x3a,0x00,0x00] +#CHECK: stcps 0(%r1) # encoding: [0xb2,0x3a,0x10,0x00] +#CHECK: stcps 0(%r15) # encoding: [0xb2,0x3a,0xf0,0x00] +#CHECK: stcps 4095 # encoding: [0xb2,0x3a,0x0f,0xff] +#CHECK: stcps 4095(%r1) # encoding: [0xb2,0x3a,0x1f,0xff] +#CHECK: stcps 4095(%r15) # encoding: [0xb2,0x3a,0xff,0xff] + + stcps 0 + stcps 0(%r1) + stcps 0(%r15) + stcps 4095 + stcps 4095(%r1) + stcps 4095(%r15) + +#CHECK: stcrw 0 # encoding: [0xb2,0x39,0x00,0x00] +#CHECK: stcrw 0(%r1) # encoding: [0xb2,0x39,0x10,0x00] +#CHECK: stcrw 0(%r15) # encoding: [0xb2,0x39,0xf0,0x00] +#CHECK: stcrw 4095 # encoding: [0xb2,0x39,0x0f,0xff] +#CHECK: stcrw 4095(%r1) # encoding: [0xb2,0x39,0x1f,0xff] +#CHECK: stcrw 4095(%r15) # encoding: [0xb2,0x39,0xff,0xff] + + stcrw 0 + stcrw 0(%r1) + stcrw 0(%r15) + stcrw 4095 + stcrw 4095(%r1) + stcrw 4095(%r15) + +#CHECK: stctg %c0, %c0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x25] +#CHECK: stctg %c0, %c15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x25] +#CHECK: stctg %c14, %c15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x25] +#CHECK: stctg %c15, %c15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x25] +#CHECK: stctg %c0, %c0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x25] +#CHECK: stctg %c0, %c0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x25] +#CHECK: stctg %c0, %c0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x25] +#CHECK: stctg %c0, %c0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x25] +#CHECK: stctg %c0, %c0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x25] +#CHECK: stctg %c0, %c0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x25] +#CHECK: stctg %c0, %c0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x25] +#CHECK: stctg %c0, %c0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x25] +#CHECK: stctg %c0, %c0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x25] + + stctg %c0,%c0,0 + stctg %c0,%c15,0 + stctg %c14,%c15,0 + stctg %c15,%c15,0 + stctg %c0,%c0,-524288 + stctg %c0,%c0,-1 + stctg %c0,%c0,0 + stctg %c0,%c0,1 + stctg %c0,%c0,524287 + stctg %c0,%c0,0(%r1) + stctg %c0,%c0,0(%r15) + stctg %c0,%c0,524287(%r1) + stctg %c0,%c0,524287(%r15) + +#CHECK: stctl %c0, %c0, 0 # encoding: [0xb6,0x00,0x00,0x00] +#CHECK: stctl %c0, %c15, 0 # encoding: [0xb6,0x0f,0x00,0x00] +#CHECK: stctl %c14, %c15, 0 # encoding: [0xb6,0xef,0x00,0x00] +#CHECK: stctl %c15, %c15, 0 # encoding: [0xb6,0xff,0x00,0x00] +#CHECK: stctl %c0, %c0, 4095 # encoding: [0xb6,0x00,0x0f,0xff] +#CHECK: stctl %c0, %c0, 1 # encoding: [0xb6,0x00,0x00,0x01] +#CHECK: stctl %c0, %c0, 0(%r1) # encoding: [0xb6,0x00,0x10,0x00] +#CHECK: stctl %c0, %c0, 0(%r15) # encoding: [0xb6,0x00,0xf0,0x00] +#CHECK: stctl %c0, %c0, 4095(%r1) # encoding: [0xb6,0x00,0x1f,0xff] +#CHECK: stctl %c0, %c0, 4095(%r15) # encoding: [0xb6,0x00,0xff,0xff] + + stctl %c0,%c0,0 + stctl %c0,%c15,0 + stctl %c14,%c15,0 + stctl %c15,%c15,0 + stctl %c0,%c0,4095 + stctl %c0,%c0,1 + stctl %c0,%c0,0(%r1) + stctl %c0,%c0,0(%r15) + stctl %c0,%c0,4095(%r1) + stctl %c0,%c0,4095(%r15) + #CHECK: stcy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x72] #CHECK: stcy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x72] #CHECK: stcy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x72] @@ -13413,6 +14544,20 @@ stey %f0, 524287(%r15,%r1) stey %f15, 0 +#CHECK: stfl 0 # encoding: [0xb2,0xb1,0x00,0x00] +#CHECK: stfl 0(%r1) # encoding: [0xb2,0xb1,0x10,0x00] +#CHECK: stfl 0(%r15) # encoding: [0xb2,0xb1,0xf0,0x00] +#CHECK: stfl 4095 # encoding: [0xb2,0xb1,0x0f,0xff] +#CHECK: stfl 4095(%r1) # encoding: [0xb2,0xb1,0x1f,0xff] +#CHECK: stfl 4095(%r15) # encoding: [0xb2,0xb1,0xff,0xff] + + stfl 0 + stfl 0(%r1) + stfl 0(%r15) + stfl 4095 + stfl 4095(%r1) + stfl 4095(%r15) + #CHECK: stfle 0 # encoding: [0xb2,0xb0,0x00,0x00] #CHECK: stfle 0(%r1) # encoding: [0xb2,0xb0,0x10,0x00] #CHECK: stfle 0(%r15) # encoding: [0xb2,0xb0,0xf0,0x00] @@ -13575,6 +14720,20 @@ sthy %r0, 524287(%r15,%r1) sthy %r15, 0 +#CHECK: stidp 0 # encoding: [0xb2,0x02,0x00,0x00] +#CHECK: stidp 0(%r1) # encoding: [0xb2,0x02,0x10,0x00] +#CHECK: stidp 0(%r15) # encoding: [0xb2,0x02,0xf0,0x00] +#CHECK: stidp 4095 # encoding: [0xb2,0x02,0x0f,0xff] +#CHECK: stidp 4095(%r1) # encoding: [0xb2,0x02,0x1f,0xff] +#CHECK: stidp 4095(%r15) # encoding: [0xb2,0x02,0xff,0xff] + + stidp 0 + stidp 0(%r1) + stidp 0(%r15) + stidp 4095 + stidp 4095(%r1) + stidp 4095(%r15) + #CHECK: stm %r0, %r0, 0 # encoding: [0x90,0x00,0x00,0x00] #CHECK: stm %r0, %r15, 0 # encoding: [0x90,0x0f,0x00,0x00] #CHECK: stm %r14, %r15, 0 # encoding: [0x90,0xef,0x00,0x00] @@ -13681,6 +14840,52 @@ stmy %r0,%r0,524287(%r1) stmy %r0,%r0,524287(%r15) +#CHECK: stnsm 0, 0 # encoding: [0xac,0x00,0x00,0x00] +#CHECK: stnsm 4095, 0 # encoding: [0xac,0x00,0x0f,0xff] +#CHECK: stnsm 0, 255 # encoding: [0xac,0xff,0x00,0x00] +#CHECK: stnsm 0(%r1), 42 # encoding: [0xac,0x2a,0x10,0x00] +#CHECK: stnsm 0(%r15), 42 # encoding: [0xac,0x2a,0xf0,0x00] +#CHECK: stnsm 4095(%r1), 42 # encoding: [0xac,0x2a,0x1f,0xff] +#CHECK: stnsm 4095(%r15), 42 # encoding: [0xac,0x2a,0xff,0xff] + + stnsm 0, 0 + stnsm 4095, 0 + stnsm 0, 255 + stnsm 0(%r1), 42 + stnsm 0(%r15), 42 + stnsm 4095(%r1), 42 + stnsm 4095(%r15), 42 + +#CHECK: stosm 0, 0 # encoding: [0xad,0x00,0x00,0x00] +#CHECK: stosm 4095, 0 # encoding: [0xad,0x00,0x0f,0xff] +#CHECK: stosm 0, 255 # encoding: [0xad,0xff,0x00,0x00] +#CHECK: stosm 0(%r1), 42 # encoding: [0xad,0x2a,0x10,0x00] +#CHECK: stosm 0(%r15), 42 # encoding: [0xad,0x2a,0xf0,0x00] +#CHECK: stosm 4095(%r1), 42 # encoding: [0xad,0x2a,0x1f,0xff] +#CHECK: stosm 4095(%r15), 42 # encoding: [0xad,0x2a,0xff,0xff] + + stosm 0, 0 + stosm 4095, 0 + stosm 0, 255 + stosm 0(%r1), 42 + stosm 0(%r15), 42 + stosm 4095(%r1), 42 + stosm 4095(%r15), 42 + +#CHECK: stpt 0 # encoding: [0xb2,0x09,0x00,0x00] +#CHECK: stpt 0(%r1) # encoding: [0xb2,0x09,0x10,0x00] +#CHECK: stpt 0(%r15) # encoding: [0xb2,0x09,0xf0,0x00] +#CHECK: stpt 4095 # encoding: [0xb2,0x09,0x0f,0xff] +#CHECK: stpt 4095(%r1) # encoding: [0xb2,0x09,0x1f,0xff] +#CHECK: stpt 4095(%r15) # encoding: [0xb2,0x09,0xff,0xff] + + stpt 0 + stpt 0(%r1) + stpt 0(%r15) + stpt 4095 + stpt 4095(%r1) + stpt 4095(%r15) + #CHECK: stpq %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x8e] #CHECK: stpq %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x8e] #CHECK: stpq %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x8e] @@ -13703,6 +14908,20 @@ stpq %r0, 524287(%r15,%r1) stpq %r14, 0 +#CHECK: stpx 0 # encoding: [0xb2,0x11,0x00,0x00] +#CHECK: stpx 0(%r1) # encoding: [0xb2,0x11,0x10,0x00] +#CHECK: stpx 0(%r15) # encoding: [0xb2,0x11,0xf0,0x00] +#CHECK: stpx 4095 # encoding: [0xb2,0x11,0x0f,0xff] +#CHECK: stpx 4095(%r1) # encoding: [0xb2,0x11,0x1f,0xff] +#CHECK: stpx 4095(%r15) # encoding: [0xb2,0x11,0xff,0xff] + + stpx 0 + stpx 0(%r1) + stpx 0(%r15) + stpx 4095 + stpx 4095(%r1) + stpx 4095(%r15) + #CHECK: strag 0, 0 # encoding: [0xe5,0x02,0x00,0x00,0x00,0x00] #CHECK: strag 0(%r1), 0(%r2) # encoding: [0xe5,0x02,0x10,0x00,0x20,0x00] #CHECK: strag 160(%r1), 320(%r15) # encoding: [0xe5,0x02,0x10,0xa0,0xf1,0x40] @@ -13828,6 +15047,54 @@ strvh %r0,524287(%r15,%r1) strvh %r15,0 +#CHECK: stsch 0 # encoding: [0xb2,0x34,0x00,0x00] +#CHECK: stsch 0(%r1) # encoding: [0xb2,0x34,0x10,0x00] +#CHECK: stsch 0(%r15) # encoding: [0xb2,0x34,0xf0,0x00] +#CHECK: stsch 4095 # encoding: [0xb2,0x34,0x0f,0xff] +#CHECK: stsch 4095(%r1) # encoding: [0xb2,0x34,0x1f,0xff] +#CHECK: stsch 4095(%r15) # encoding: [0xb2,0x34,0xff,0xff] + + stsch 0 + stsch 0(%r1) + stsch 0(%r15) + stsch 4095 + stsch 4095(%r1) + stsch 4095(%r15) + +#CHECK: stsi 0 # encoding: [0xb2,0x7d,0x00,0x00] +#CHECK: stsi 0(%r1) # encoding: [0xb2,0x7d,0x10,0x00] +#CHECK: stsi 0(%r15) # encoding: [0xb2,0x7d,0xf0,0x00] +#CHECK: stsi 4095 # encoding: [0xb2,0x7d,0x0f,0xff] +#CHECK: stsi 4095(%r1) # encoding: [0xb2,0x7d,0x1f,0xff] +#CHECK: stsi 4095(%r15) # encoding: [0xb2,0x7d,0xff,0xff] + + stsi 0 + stsi 0(%r1) + stsi 0(%r15) + stsi 4095 + stsi 4095(%r1) + stsi 4095(%r15) + +#CHECK: stura %r0, %r0 # encoding: [0xb2,0x46,0x00,0x00] +#CHECK: stura %r0, %r15 # encoding: [0xb2,0x46,0x00,0x0f] +#CHECK: stura %r15, %r0 # encoding: [0xb2,0x46,0x00,0xf0] +#CHECK: stura %r7, %r8 # encoding: [0xb2,0x46,0x00,0x78] + + stura %r0,%r0 + stura %r0,%r15 + stura %r15,%r0 + stura %r7,%r8 + +#CHECK: sturg %r0, %r0 # encoding: [0xb9,0x25,0x00,0x00] +#CHECK: sturg %r0, %r15 # encoding: [0xb9,0x25,0x00,0x0f] +#CHECK: sturg %r15, %r0 # encoding: [0xb9,0x25,0x00,0xf0] +#CHECK: sturg %r7, %r8 # encoding: [0xb9,0x25,0x00,0x78] + + sturg %r0,%r0 + sturg %r0,%r15 + sturg %r15,%r0 + sturg %r7,%r8 + #CHECK: sty %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x50] #CHECK: sty %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x50] #CHECK: sty %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x50] @@ -13970,6 +15237,28 @@ tam +#CHECK: tar %a0, %r0 # encoding: [0xb2,0x4c,0x00,0x00] +#CHECK: tar %a0, %r15 # encoding: [0xb2,0x4c,0x00,0x0f] +#CHECK: tar %a15, %r0 # encoding: [0xb2,0x4c,0x00,0xf0] +#CHECK: tar %a7, %r8 # encoding: [0xb2,0x4c,0x00,0x78] + + tar %a0,%r0 + tar %a0,%r15 + tar %a15,%r0 + tar %a7,%r8 + +#CHECK: tb %r0, %r0 # encoding: [0xb2,0x2c,0x00,0x00] +#CHECK: tb %r0, %r15 # encoding: [0xb2,0x2c,0x00,0x0f] +#CHECK: tb %r15, %r0 # encoding: [0xb2,0x2c,0x00,0xf0] +#CHECK: tb %r7, %r8 # encoding: [0xb2,0x2c,0x00,0x78] +#CHECK: tb %r15, %r15 # encoding: [0xb2,0x2c,0x00,0xff] + + tb %r0,%r0 + tb %r0,%r15 + tb %r15,%r0 + tb %r7,%r8 + tb %r15,%r15 + #CHECK: tbdr %f0, 0, %f0 # encoding: [0xb3,0x51,0x00,0x00] #CHECK: tbdr %f0, 0, %f15 # encoding: [0xb3,0x51,0x00,0x0f] #CHECK: tbdr %f0, 15, %f0 # encoding: [0xb3,0x51,0xf0,0x00] @@ -14272,6 +15561,42 @@ tp 0(16,%r1) tp 0(16,%r15) +#CHECK: tpi 0 # encoding: [0xb2,0x36,0x00,0x00] +#CHECK: tpi 0(%r1) # encoding: [0xb2,0x36,0x10,0x00] +#CHECK: tpi 0(%r15) # encoding: [0xb2,0x36,0xf0,0x00] +#CHECK: tpi 4095 # encoding: [0xb2,0x36,0x0f,0xff] +#CHECK: tpi 4095(%r1) # encoding: [0xb2,0x36,0x1f,0xff] +#CHECK: tpi 4095(%r15) # encoding: [0xb2,0x36,0xff,0xff] + + tpi 0 + tpi 0(%r1) + tpi 0(%r15) + tpi 4095 + tpi 4095(%r1) + tpi 4095(%r15) + +#CHECK: tprot 0, 0 # encoding: [0xe5,0x01,0x00,0x00,0x00,0x00] +#CHECK: tprot 0(%r1), 0(%r2) # encoding: [0xe5,0x01,0x10,0x00,0x20,0x00] +#CHECK: tprot 160(%r1), 320(%r15) # encoding: [0xe5,0x01,0x10,0xa0,0xf1,0x40] +#CHECK: tprot 0(%r1), 4095 # encoding: [0xe5,0x01,0x10,0x00,0x0f,0xff] +#CHECK: tprot 0(%r1), 4095(%r2) # encoding: [0xe5,0x01,0x10,0x00,0x2f,0xff] +#CHECK: tprot 0(%r1), 4095(%r15) # encoding: [0xe5,0x01,0x10,0x00,0xff,0xff] +#CHECK: tprot 0(%r1), 0 # encoding: [0xe5,0x01,0x10,0x00,0x00,0x00] +#CHECK: tprot 0(%r15), 0 # encoding: [0xe5,0x01,0xf0,0x00,0x00,0x00] +#CHECK: tprot 4095(%r1), 0 # encoding: [0xe5,0x01,0x1f,0xff,0x00,0x00] +#CHECK: tprot 4095(%r15), 0 # encoding: [0xe5,0x01,0xff,0xff,0x00,0x00] + + tprot 0, 0 + tprot 0(%r1), 0(%r2) + tprot 160(%r1), 320(%r15) + tprot 0(%r1), 4095 + tprot 0(%r1), 4095(%r2) + tprot 0(%r1), 4095(%r15) + tprot 0(%r1), 0 + tprot 0(%r15), 0 + tprot 4095(%r1), 0 + tprot 4095(%r15), 0 + #CHECK: tr 0(1), 0 # encoding: [0xdc,0x00,0x00,0x00,0x00,0x00] #CHECK: tr 0(1), 0(%r1) # encoding: [0xdc,0x00,0x00,0x00,0x10,0x00] #CHECK: tr 0(1), 0(%r15) # encoding: [0xdc,0x00,0x00,0x00,0xf0,0x00] @@ -14298,6 +15623,74 @@ tr 0(256,%r1), 0 tr 0(256,%r15), 0 +#CHECK: trace %r0, %r0, 0 # encoding: [0x99,0x00,0x00,0x00] +#CHECK: trace %r0, %r15, 0 # encoding: [0x99,0x0f,0x00,0x00] +#CHECK: trace %r14, %r15, 0 # encoding: [0x99,0xef,0x00,0x00] +#CHECK: trace %r15, %r15, 0 # encoding: [0x99,0xff,0x00,0x00] +#CHECK: trace %r0, %r0, 4095 # encoding: [0x99,0x00,0x0f,0xff] +#CHECK: trace %r0, %r0, 1 # encoding: [0x99,0x00,0x00,0x01] +#CHECK: trace %r0, %r0, 0(%r1) # encoding: [0x99,0x00,0x10,0x00] +#CHECK: trace %r0, %r0, 0(%r15) # encoding: [0x99,0x00,0xf0,0x00] +#CHECK: trace %r0, %r0, 4095(%r1) # encoding: [0x99,0x00,0x1f,0xff] +#CHECK: trace %r0, %r0, 4095(%r15) # encoding: [0x99,0x00,0xff,0xff] + + trace %r0,%r0,0 + trace %r0,%r15,0 + trace %r14,%r15,0 + trace %r15,%r15,0 + trace %r0,%r0,4095 + trace %r0,%r0,1 + trace %r0,%r0,0(%r1) + trace %r0,%r0,0(%r15) + trace %r0,%r0,4095(%r1) + trace %r0,%r0,4095(%r15) + +#CHECK: tracg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x0f] +#CHECK: tracg %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x0f] +#CHECK: tracg %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x0f] +#CHECK: tracg %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x0f] +#CHECK: tracg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x0f] +#CHECK: tracg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x0f] +#CHECK: tracg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x0f] +#CHECK: tracg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x0f] +#CHECK: tracg %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x0f] +#CHECK: tracg %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x0f] +#CHECK: tracg %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x0f] +#CHECK: tracg %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x0f] +#CHECK: tracg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x0f] + + tracg %r0,%r0,0 + tracg %r0,%r15,0 + tracg %r14,%r15,0 + tracg %r15,%r15,0 + tracg %r0,%r0,-524288 + tracg %r0,%r0,-1 + tracg %r0,%r0,0 + tracg %r0,%r0,1 + tracg %r0,%r0,524287 + tracg %r0,%r0,0(%r1) + tracg %r0,%r0,0(%r15) + tracg %r0,%r0,524287(%r1) + tracg %r0,%r0,524287(%r15) + +#CHECK: trap2 # encoding: [0x01,0xff] + + trap2 + +#CHECK: trap4 0 # encoding: [0xb2,0xff,0x00,0x00] +#CHECK: trap4 0(%r1) # encoding: [0xb2,0xff,0x10,0x00] +#CHECK: trap4 0(%r15) # encoding: [0xb2,0xff,0xf0,0x00] +#CHECK: trap4 4095 # encoding: [0xb2,0xff,0x0f,0xff] +#CHECK: trap4 4095(%r1) # encoding: [0xb2,0xff,0x1f,0xff] +#CHECK: trap4 4095(%r15) # encoding: [0xb2,0xff,0xff,0xff] + + trap4 0 + trap4 0(%r1) + trap4 0(%r15) + trap4 4095 + trap4 4095(%r1) + trap4 4095(%r15) + #CHECK: tre %r0, %r0 # encoding: [0xb2,0xa5,0x00,0x00] #CHECK: tre %r0, %r15 # encoding: [0xb2,0xa5,0x00,0x0f] #CHECK: tre %r14, %r0 # encoding: [0xb2,0xa5,0x00,0xe0] @@ -14458,6 +15851,20 @@ ts 4095(%r1) ts 4095(%r15) +#CHECK: tsch 0 # encoding: [0xb2,0x35,0x00,0x00] +#CHECK: tsch 0(%r1) # encoding: [0xb2,0x35,0x10,0x00] +#CHECK: tsch 0(%r15) # encoding: [0xb2,0x35,0xf0,0x00] +#CHECK: tsch 4095 # encoding: [0xb2,0x35,0x0f,0xff] +#CHECK: tsch 4095(%r1) # encoding: [0xb2,0x35,0x1f,0xff] +#CHECK: tsch 4095(%r15) # encoding: [0xb2,0x35,0xff,0xff] + + tsch 0 + tsch 0(%r1) + tsch 0(%r15) + tsch 4095 + tsch 4095(%r1) + tsch 4095(%r15) + #CHECK: unpk 0(1), 0(1) # encoding: [0xf3,0x00,0x00,0x00,0x00,0x00] #CHECK: unpk 0(1), 0(1,%r1) # encoding: [0xf3,0x00,0x00,0x00,0x10,0x00] #CHECK: unpk 0(1), 0(1,%r15) # encoding: [0xf3,0x00,0x00,0x00,0xf0,0x00] @@ -14682,6 +16089,10 @@ xr %r15,%r0 xr %r7,%r8 +#CHECK: xsch # encoding: [0xb2,0x76,0x00,0x00] + + xsch + #CHECK: xy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x57] #CHECK: xy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x57] #CHECK: xy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x57] diff --git a/llvm/test/MC/SystemZ/regs-bad.s b/llvm/test/MC/SystemZ/regs-bad.s index 37c83dd4b8f..f4cdb69821d 100644 --- a/llvm/test/MC/SystemZ/regs-bad.s +++ b/llvm/test/MC/SystemZ/regs-bad.s @@ -8,18 +8,24 @@ #CHECK: error: invalid operand for instruction #CHECK: lr %a0,%r1 #CHECK: error: invalid operand for instruction +#CHECK: lr %c0,%r1 +#CHECK: error: invalid operand for instruction #CHECK: lr %r0,%f1 #CHECK: error: invalid operand for instruction #CHECK: lr %r0,%a1 #CHECK: error: invalid operand for instruction +#CHECK: lr %r0,%c1 +#CHECK: error: invalid operand for instruction #CHECK: lr %r0,0 #CHECK: error: invalid operand for instruction #CHECK: lr %r0,0(%r1) lr %f0,%r1 lr %a0,%r1 + lr %c0,%r1 lr %r0,%f1 lr %r0,%a1 + lr %r0,%c1 lr %r0,0 lr %r0,0(%r1) @@ -30,18 +36,24 @@ #CHECK: error: invalid operand for instruction #CHECK: lgr %a0,%r1 #CHECK: error: invalid operand for instruction +#CHECK: lgr %c0,%r1 +#CHECK: error: invalid operand for instruction #CHECK: lgr %r0,%f1 #CHECK: error: invalid operand for instruction #CHECK: lgr %r0,%a1 #CHECK: error: invalid operand for instruction +#CHECK: lgr %r0,%c1 +#CHECK: error: invalid operand for instruction #CHECK: lgr %r0,0 #CHECK: error: invalid operand for instruction #CHECK: lgr %r0,0(%r1) lgr %f0,%r1 lgr %a0,%r1 + lgr %c0,%r1 lgr %r0,%f1 lgr %r0,%a1 + lgr %r0,%c1 lgr %r0,0 lgr %r0,0(%r1) @@ -68,10 +80,14 @@ #CHECK: error: invalid operand for instruction #CHECK: dlr %a0,%r1 #CHECK: error: invalid operand for instruction +#CHECK: dlr %c0,%r1 +#CHECK: error: invalid operand for instruction #CHECK: dlr %r0,%f1 #CHECK: error: invalid operand for instruction #CHECK: dlr %r0,%a1 #CHECK: error: invalid operand for instruction +#CHECK: dlr %r0,%c1 +#CHECK: error: invalid operand for instruction #CHECK: dlr %r0,0 #CHECK: error: invalid operand for instruction #CHECK: dlr %r0,0(%r1) @@ -86,8 +102,10 @@ dlr %r15,%r0 dlr %f0,%r1 dlr %a0,%r1 + dlr %c0,%r1 dlr %r0,%f1 dlr %r0,%a1 + dlr %r0,%c1 dlr %r0,0 dlr %r0,0(%r1) @@ -98,18 +116,24 @@ #CHECK: error: invalid operand for instruction #CHECK: ler %a0,%f1 #CHECK: error: invalid operand for instruction +#CHECK: ler %c0,%f1 +#CHECK: error: invalid operand for instruction #CHECK: ler %f0,%r1 #CHECK: error: invalid operand for instruction #CHECK: ler %f0,%a1 #CHECK: error: invalid operand for instruction +#CHECK: ler %f0,%c1 +#CHECK: error: invalid operand for instruction #CHECK: ler %f0,0 #CHECK: error: invalid operand for instruction #CHECK: ler %f0,0(%r1) ler %r0,%f1 ler %a0,%f1 + ler %c0,%f1 ler %f0,%r1 ler %f0,%a1 + ler %f0,%c1 ler %f0,0 ler %f0,0(%r1) @@ -120,18 +144,24 @@ #CHECK: error: invalid operand for instruction #CHECK: ldr %a0,%f1 #CHECK: error: invalid operand for instruction +#CHECK: ldr %c0,%f1 +#CHECK: error: invalid operand for instruction #CHECK: ldr %f0,%r1 #CHECK: error: invalid operand for instruction #CHECK: ldr %f0,%a1 #CHECK: error: invalid operand for instruction +#CHECK: ldr %f0,%c1 +#CHECK: error: invalid operand for instruction #CHECK: ldr %f0,0 #CHECK: error: invalid operand for instruction #CHECK: ldr %f0,0(%r1) ldr %r0,%f1 ldr %a0,%f1 + ldr %c0,%f1 ldr %f0,%r1 ldr %f0,%a1 + ldr %f0,%c1 ldr %f0,0 ldr %f0,0(%r1) @@ -158,10 +188,14 @@ #CHECK: error: invalid operand for instruction #CHECK: lxr %a0,%f1 #CHECK: error: invalid operand for instruction +#CHECK: lxr %c0,%f1 +#CHECK: error: invalid operand for instruction #CHECK: lxr %f0,%r1 #CHECK: error: invalid operand for instruction #CHECK: lxr %f0,%a1 #CHECK: error: invalid operand for instruction +#CHECK: lxr %f0,%c1 +#CHECK: error: invalid operand for instruction #CHECK: lxr %f0,0 #CHECK: error: invalid operand for instruction #CHECK: lxr %f0,0(%r1) @@ -176,8 +210,10 @@ lxr %f0,%f15 lxr %r0,%f1 lxr %a0,%f1 + lxr %c0,%f1 lxr %f0,%r1 lxr %f0,%a1 + lxr %f0,%c1 lxr %f0,0 lxr %f0,0(%r1) @@ -188,15 +224,33 @@ #CHECK: error: invalid operand for instruction #CHECK: ear %r0,%f0 #CHECK: error: invalid operand for instruction +#CHECK: ear %r0,%c0 +#CHECK: error: invalid operand for instruction #CHECK: ear %r0,0 #CHECK: error: invalid operand for instruction #CHECK: ear %r0,0(%r1) ear %r0,%r0 ear %r0,%f0 + ear %r0,%c0 ear %r0,0 ear %r0,0(%r1) +# Test control register operands +# +#CHECK: error: invalid operand for instruction +#CHECK: lctl %c0,%r0,0 +#CHECK: lctl %c0,%f0,0 +#CHECK: lctl %c0,%a0,0 +#CHECK: lctl %c0,0,0 +#CHECK: lctl %c0,0(%r1),0 + + lctl %c0,%r0,0 + lctl %c0,%f0,0 + lctl %c0,%a0,0 + lctl %c0,0,0 + lctl %c0,0(%r1),0 + .cfi_startproc # Test general register parsing, with no predetermined class in mind. @@ -212,9 +266,9 @@ #CHECK: error: invalid register #CHECK: .cfi_offset %a,0 #CHECK: error: invalid register -#CHECK: .cfi_offset %0,0 +#CHECK: .cfi_offset %c,0 #CHECK: error: invalid register -#CHECK: .cfi_offset %c0,0 +#CHECK: .cfi_offset %0,0 #CHECK: error: invalid register #CHECK: .cfi_offset %r16,0 #CHECK: error: invalid register @@ -222,6 +276,8 @@ #CHECK: error: invalid register #CHECK: .cfi_offset %a16,0 #CHECK: error: invalid register +#CHECK: .cfi_offset %c16,0 +#CHECK: error: invalid register #CHECK: .cfi_offset %reef,0 #CHECK: error: invalid register #CHECK: .cfi_offset %arid,0 @@ -231,11 +287,12 @@ .cfi_offset %r,0 .cfi_offset %f,0 .cfi_offset %a,0 + .cfi_offset %c,0 .cfi_offset %0,0 - .cfi_offset %c0,0 .cfi_offset %r16,0 .cfi_offset %f16,0 .cfi_offset %a16,0 + .cfi_offset %c16,0 .cfi_offset %reef,0 .cfi_offset %arid,0 diff --git a/llvm/test/MC/SystemZ/regs-good.s b/llvm/test/MC/SystemZ/regs-good.s index 4047579bcbb..c20301133d8 100644 --- a/llvm/test/MC/SystemZ/regs-good.s +++ b/llvm/test/MC/SystemZ/regs-good.s @@ -118,6 +118,25 @@ cpya %a12,%a13 cpya %a14,%a15 +#CHECK: lctl %c0, %c1, 0 # encoding: [0xb7,0x01,0x00,0x00] +#CHECK: lctl %c2, %c3, 0 # encoding: [0xb7,0x23,0x00,0x00] +#CHECK: lctl %c4, %c5, 0 # encoding: [0xb7,0x45,0x00,0x00] +#CHECK: lctl %c6, %c7, 0 # encoding: [0xb7,0x67,0x00,0x00] +#CHECK: lctl %c8, %c9, 0 # encoding: [0xb7,0x89,0x00,0x00] +#CHECK: lctl %c10, %c11, 0 # encoding: [0xb7,0xab,0x00,0x00] +#CHECK: lctl %c12, %c13, 0 # encoding: [0xb7,0xcd,0x00,0x00] +#CHECK: lctl %c14, %c15, 0 # encoding: [0xb7,0xef,0x00,0x00] + + lctl %c0,%c1,0 + lctl %c2,%c3,0 + lctl %c4,%c5,0 + lctl %c6,%c7,0 + lctl %c8,%c9,0 + lctl %c10,%c11,0 + lctl %c12,%c13,0 + lctl %c14,%c15,0 + + #CHECK: .cfi_offset %r0, 0 #CHECK: .cfi_offset %r1, 8 #CHECK: .cfi_offset %r2, 16 @@ -166,6 +185,22 @@ #CHECK: .cfi_offset %a13, 308 #CHECK: .cfi_offset %a14, 312 #CHECK: .cfi_offset %a15, 316 +#CHECK: .cfi_offset %c0, 318 +#CHECK: .cfi_offset %c1, 326 +#CHECK: .cfi_offset %c2, 334 +#CHECK: .cfi_offset %c3, 342 +#CHECK: .cfi_offset %c4, 350 +#CHECK: .cfi_offset %c5, 358 +#CHECK: .cfi_offset %c6, 366 +#CHECK: .cfi_offset %c7, 374 +#CHECK: .cfi_offset %c8, 382 +#CHECK: .cfi_offset %c9, 390 +#CHECK: .cfi_offset %c10, 398 +#CHECK: .cfi_offset %c11, 406 +#CHECK: .cfi_offset %c12, 414 +#CHECK: .cfi_offset %c13, 422 +#CHECK: .cfi_offset %c14, 430 +#CHECK: .cfi_offset %c15, 438 .cfi_startproc .cfi_offset %r0,0 @@ -216,4 +251,20 @@ .cfi_offset %a13,308 .cfi_offset %a14,312 .cfi_offset %a15,316 + .cfi_offset %c0,318 + .cfi_offset %c1,326 + .cfi_offset %c2,334 + .cfi_offset %c3,342 + .cfi_offset %c4,350 + .cfi_offset %c5,358 + .cfi_offset %c6,366 + .cfi_offset %c7,374 + .cfi_offset %c8,382 + .cfi_offset %c9,390 + .cfi_offset %c10,398 + .cfi_offset %c11,406 + .cfi_offset %c12,414 + .cfi_offset %c13,422 + .cfi_offset %c14,430 + .cfi_offset %c15,438 .cfi_endproc |
