Allows instructions which no explicit operands. e.g. X86 RET which has but

an implicit flag operand.

llvm-svn: 24916

1 files changed, 5 insertions, 6 deletions

diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index be8fb75b43a..140c8f2bf12 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -1124,23 +1124,22 @@ void DAGISelEmitter::ParseInstructions() {
       std::vector<Record*> Operands;
       
       CodeGenInstruction &InstInfo =Target.getInstruction(Instrs[i]->getName());
-      
-      // Doesn't even define a result?
-      if (InstInfo.OperandList.size() == 0)
-        continue;
 
+      // Note: Removed if (InstInfo.OperandList.size() == 0) continue;
+      // It's possible for some instruction, e.g. RET for X86 that only has an
+      // implicit flag operand.
       // FIXME: temporary hack...
       if (InstInfo.isReturn || InstInfo.isBranch || InstInfo.isCall ||
           InstInfo.isStore) {
         // These produce no results
-        for (unsigned j = 0, e = InstInfo.OperandList.size(); j != e; ++j)
+        for (unsigned j = 0, e = InstInfo.OperandList.size(); j < e; ++j)
           Operands.push_back(InstInfo.OperandList[j].Rec);
       } else {
         // Assume the first operand is the result.
         Results.push_back(InstInfo.OperandList[0].Rec);
       
         // The rest are inputs.
-        for (unsigned j = 1, e = InstInfo.OperandList.size(); j != e; ++j)
+        for (unsigned j = 1, e = InstInfo.OperandList.size(); j < e; ++j)
           Operands.push_back(InstInfo.OperandList[j].Rec);
       }