diff options
| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2013-05-31 23:45:26 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2013-05-31 23:45:26 +0000 |
| commit | b1a4d9da3b7d48c40e6abee2acc9f6324dad7f84 (patch) | |
| tree | 9c40c9ccfbe5f8ef21d580220db6d0f82ec1764d /llvm/utils | |
| parent | ee9143acf503e487f62423594ce52525e28ced9f (diff) | |
| download | bcm5719-llvm-b1a4d9da3b7d48c40e6abee2acc9f6324dad7f84.tar.gz bcm5719-llvm-b1a4d9da3b7d48c40e6abee2acc9f6324dad7f84.zip | |
Make SubRegIndex size mandatory, following r183020.
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
llvm-svn: 183061
Diffstat (limited to 'llvm/utils')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenRegisters.cpp | 15 | ||||
| -rw-r--r-- | llvm/utils/TableGen/CodeGenRegisters.h | 6 | ||||
| -rw-r--r-- | llvm/utils/TableGen/RegisterInfoEmitter.cpp | 4 |
3 files changed, 18 insertions, 7 deletions
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp index 3eed3ffb5f4..daa7eab658d 100644 --- a/llvm/utils/TableGen/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/CodeGenRegisters.cpp @@ -1092,11 +1092,24 @@ getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts) { // None exists, synthesize one. std::string Name = Parts.front()->getName(); + // Determine whether all parts are contiguous. + bool isContinuous = true; + unsigned Size = Parts.front()->Size; + unsigned LastOffset = Parts.front()->Offset; + unsigned LastSize = Parts.front()->Size; for (unsigned i = 1, e = Parts.size(); i != e; ++i) { Name += '_'; Name += Parts[i]->getName(); + Size += Parts[i]->Size; + if (Parts[i]->Offset != (LastOffset + LastSize)) + isContinuous = false; + LastOffset = Parts[i]->Offset; + LastSize = Parts[i]->Size; } - return Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); + Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); + Idx->Size = Size; + Idx->Offset = isContinuous ? Parts.front()->Offset : -1; + return Idx; } void CodeGenRegBank::computeComposites() { diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h index c83455149a6..f9edc6553ac 100644 --- a/llvm/utils/TableGen/CodeGenRegisters.h +++ b/llvm/utils/TableGen/CodeGenRegisters.h @@ -37,10 +37,10 @@ namespace llvm { Record *const TheDef; std::string Name; std::string Namespace; - uint16_t Size; - uint16_t Offset; public: + uint16_t Size; + uint16_t Offset; const unsigned EnumValue; unsigned LaneMask; @@ -54,8 +54,6 @@ namespace llvm { const std::string &getName() const { return Name; } const std::string &getNamespace() const { return Namespace; } std::string getQualifiedName() const; - uint16_t getSize() const { return Size; } - uint16_t getOffset() const { return Offset; } // Order CodeGenSubRegIndex pointers by EnumValue. struct Less { diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index 9978237a185..1a6cc3a01c2 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -798,8 +798,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, for (ArrayRef<CodeGenSubRegIndex*>::const_iterator SRI = SubRegIndices.begin(), SRE = SubRegIndices.end(); SRI != SRE; ++SRI) { - OS << " { " << (*SRI)->getOffset() << ", " - << (*SRI)->getSize() + OS << " { " << (*SRI)->Offset << ", " + << (*SRI)->Size << " },\t// " << (*SRI)->getName() << "\n"; } OS << "};\n\n"; |

