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authorQuentin Colombet <qcolombet@apple.com>2014-08-20 23:49:36 +0000
committerQuentin Colombet <qcolombet@apple.com>2014-08-20 23:49:36 +0000
commit7e3da6677a4239da77ea83e7005a603618e7a725 (patch)
tree6ffcec69fcaaaf80a4ea604ee8f617bdbd9b3231 /llvm/utils
parent44937d98a30c5ad8b6fdcdfece07228b159fbf24 (diff)
downloadbcm5719-llvm-7e3da6677a4239da77ea83e7005a603618e7a725.tar.gz
bcm5719-llvm-7e3da6677a4239da77ea83e7005a603618e7a725.zip
Add isInsertSubreg property.
This patch adds a new property: isInsertSubreg and the related target hooks: TargetIntrInfo::getInsertSubregInputs and TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific instruction is a (kind of) INSERT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216139
Diffstat (limited to 'llvm/utils')
-rw-r--r--llvm/utils/TableGen/CodeGenInstruction.cpp1
-rw-r--r--llvm/utils/TableGen/CodeGenInstruction.h1
-rw-r--r--llvm/utils/TableGen/InstrInfoEmitter.cpp1
3 files changed, 3 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/CodeGenInstruction.cpp b/llvm/utils/TableGen/CodeGenInstruction.cpp
index 20edef5a71c..d567ddea58b 100644
--- a/llvm/utils/TableGen/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/CodeGenInstruction.cpp
@@ -316,6 +316,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
isNotDuplicable = R->getValueAsBit("isNotDuplicable");
isRegSequence = R->getValueAsBit("isRegSequence");
isExtractSubreg = R->getValueAsBit("isExtractSubreg");
+ isInsertSubreg = R->getValueAsBit("isInsertSubreg");
bool Unset;
mayLoad = R->getValueAsBitOrUnset("mayLoad", Unset);
diff --git a/llvm/utils/TableGen/CodeGenInstruction.h b/llvm/utils/TableGen/CodeGenInstruction.h
index 649fbc29ce7..92aac5fed33 100644
--- a/llvm/utils/TableGen/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/CodeGenInstruction.h
@@ -255,6 +255,7 @@ namespace llvm {
bool isPseudo : 1;
bool isRegSequence : 1;
bool isExtractSubreg : 1;
+ bool isInsertSubreg : 1;
std::string DeprecatedReason;
bool HasComplexDeprecationPredicate;
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 86578a84d96..6fdf22dd678 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -507,6 +507,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
if (Inst.isRegSequence) OS << "|(1<<MCID::RegSequence)";
if (Inst.isExtractSubreg) OS << "|(1<<MCID::ExtractSubreg)";
+ if (Inst.isInsertSubreg) OS << "|(1<<MCID::InsertSubreg)";
// Emit all of the target-specific flags...
BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
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