gn build: Fewer dependencies in llvm/lib/Target

The tablegen groups only need public_deps for inc files included
(possibly transitively) in other targets. Move inc files that are
internan to the MCTargetDesc libraries into regular deps.

Related to the changes that merged InstPrinter into MCTargetDesc
(360484, 360486 etc).

llvm-svn: 360600

6 files changed, 44 insertions, 26 deletions

diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn
index 65fa23c2581..6336416b927 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn
@@ -1,13 +1,13 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("AArch64GenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../AArch64.td"
 }
 
 tablegen("AArch64GenAsmWriter1") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [
     "-gen-asm-writer",
     "-asmwriternum=1",
@@ -22,7 +22,7 @@ tablegen("AArch64GenInstrInfo") {
 }
 
 tablegen("AArch64GenMCCodeEmitter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-emitter" ]
   td_file = "../AArch64.td"
 }
@@ -39,6 +39,9 @@ tablegen("AArch64GenSubtargetInfo") {
   td_file = "../AArch64.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
@@ -46,10 +49,7 @@ group("tablegen") {
     "../Utils",
   ]
   public_deps = [
-    ":AArch64GenAsmWriter",
-    ":AArch64GenAsmWriter1",
     ":AArch64GenInstrInfo",
-    ":AArch64GenMCCodeEmitter",
     ":AArch64GenRegisterInfo",
     ":AArch64GenSubtargetInfo",
   ]
@@ -61,6 +61,9 @@ static_library("MCTargetDesc") {
     ":tablegen",
   ]
   deps = [
+    ":AArch64GenAsmWriter",
+    ":AArch64GenAsmWriter1",
+    ":AArch64GenMCCodeEmitter",
     "//llvm/lib/MC",
     "//llvm/lib/Support",
     "//llvm/lib/Target/AArch64/TargetInfo",
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/ARM/MCTargetDesc/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/MCTargetDesc/BUILD.gn
index 185f2cb7aa2..098e2ab5aaf 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/ARM/MCTargetDesc/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/MCTargetDesc/BUILD.gn
@@ -1,7 +1,7 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("ARMGenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../ARM.td"
 }
@@ -13,7 +13,7 @@ tablegen("ARMGenInstrInfo") {
 }
 
 tablegen("ARMGenMCCodeEmitter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-emitter" ]
   td_file = "../ARM.td"
 }
@@ -30,6 +30,9 @@ tablegen("ARMGenSubtargetInfo") {
   td_file = "../ARM.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
@@ -37,9 +40,7 @@ group("tablegen") {
     "../Utils",
   ]
   public_deps = [
-    ":ARMGenAsmWriter",
     ":ARMGenInstrInfo",
-    ":ARMGenMCCodeEmitter",
     ":ARMGenRegisterInfo",
     ":ARMGenSubtargetInfo",
   ]
@@ -50,6 +51,8 @@ static_library("MCTargetDesc") {
     ":tablegen",
   ]
   deps = [
+    ":ARMGenAsmWriter",
+    ":ARMGenMCCodeEmitter",
     "//llvm/lib/MC",
     "//llvm/lib/MC/MCDisassembler",
     "//llvm/lib/Support",
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/MCTargetDesc/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/MCTargetDesc/BUILD.gn
index ce00e5a8486..6c31eb48750 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/MCTargetDesc/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/MCTargetDesc/BUILD.gn
@@ -1,7 +1,7 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("BPFGenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../BPF.td"
 }
@@ -13,7 +13,7 @@ tablegen("BPFGenInstrInfo") {
 }
 
 tablegen("BPFGenMCCodeEmitter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-emitter" ]
   td_file = "../BPF.td"
 }
@@ -30,15 +30,16 @@ tablegen("BPFGenSubtargetInfo") {
   td_file = "../BPF.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
     "../TargetInfo",
   ]
   public_deps = [
-    ":BPFGenAsmWriter",
     ":BPFGenInstrInfo",
-    ":BPFGenMCCodeEmitter",
     ":BPFGenRegisterInfo",
     ":BPFGenSubtargetInfo",
   ]
@@ -50,6 +51,8 @@ static_library("MCTargetDesc") {
     ":tablegen",
   ]
   deps = [
+    ":BPFGenAsmWriter",
+    ":BPFGenMCCodeEmitter",
     "//llvm/lib/MC",
     "//llvm/lib/MC/MCDisassembler",
     "//llvm/lib/Support",
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/MCTargetDesc/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/MCTargetDesc/BUILD.gn
index 4fafcb60350..4bc058db553 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/MCTargetDesc/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/MCTargetDesc/BUILD.gn
@@ -1,7 +1,7 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("PPCGenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../PPC.td"
 }
@@ -13,7 +13,7 @@ tablegen("PPCGenInstrInfo") {
 }
 
 tablegen("PPCGenMCCodeEmitter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-emitter" ]
   td_file = "../PPC.td"
 }
@@ -30,6 +30,9 @@ tablegen("PPCGenSubtargetInfo") {
   td_file = "../PPC.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
@@ -37,9 +40,7 @@ group("tablegen") {
     "../TargetInfo",
   ]
   public_deps = [
-    ":PPCGenAsmWriter",
     ":PPCGenInstrInfo",
-    ":PPCGenMCCodeEmitter",
     ":PPCGenRegisterInfo",
     ":PPCGenSubtargetInfo",
   ]
@@ -51,6 +52,8 @@ static_library("MCTargetDesc") {
     ":tablegen",
   ]
   deps = [
+    ":PPCGenAsmWriter",
+    ":PPCGenMCCodeEmitter",
     "//llvm/lib/MC",
     "//llvm/lib/Support",
     "//llvm/lib/Target/PowerPC/TargetInfo",
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/MCTargetDesc/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/MCTargetDesc/BUILD.gn
index bf106cde9c4..326525cd42b 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/MCTargetDesc/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/MCTargetDesc/BUILD.gn
@@ -1,7 +1,7 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("WebAssemblyGenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../WebAssembly.td"
 }
@@ -13,7 +13,7 @@ tablegen("WebAssemblyGenInstrInfo") {
 }
 
 tablegen("WebAssemblyGenMCCodeEmitter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-emitter" ]
   td_file = "../WebAssembly.td"
 }
@@ -30,6 +30,9 @@ tablegen("WebAssemblyGenSubtargetInfo") {
   td_file = "../WebAssembly.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
@@ -38,9 +41,7 @@ group("tablegen") {
     "../Utils",
   ]
   public_deps = [
-    ":WebAssemblyGenAsmWriter",
     ":WebAssemblyGenInstrInfo",
-    ":WebAssemblyGenMCCodeEmitter",
     ":WebAssemblyGenRegisterInfo",
     ":WebAssemblyGenSubtargetInfo",
   ]
@@ -51,6 +52,8 @@ static_library("MCTargetDesc") {
     ":tablegen",
   ]
   deps = [
+    ":WebAssemblyGenAsmWriter",
+    ":WebAssemblyGenMCCodeEmitter",
     "//llvm/lib/MC",
     "//llvm/lib/Support",
     "//llvm/lib/Target/WebAssembly/TargetInfo",
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn
index e493d867860..05747037d04 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn
@@ -1,13 +1,13 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("X86GenAsmWriter") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [ "-gen-asm-writer" ]
   td_file = "../X86.td"
 }
 
 tablegen("X86GenAsmWriter1") {
-  visibility = [ ":tablegen" ]
+  visibility = [ ":MCTargetDesc" ]
   args = [
     "-gen-asm-writer",
     "-asmwriternum=1",
@@ -33,14 +33,15 @@ tablegen("X86GenSubtargetInfo") {
   td_file = "../X86.td"
 }
 
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
 group("tablegen") {
   visibility = [
     ":MCTargetDesc",
     "../TargetInfo",
   ]
   public_deps = [
-    ":X86GenAsmWriter",
-    ":X86GenAsmWriter1",
     ":X86GenInstrInfo",
     ":X86GenRegisterInfo",
     ":X86GenSubtargetInfo",
@@ -53,6 +54,8 @@ static_library("MCTargetDesc") {
     ":tablegen",
   ]
   deps = [
+    ":X86GenAsmWriter",
+    ":X86GenAsmWriter1",
     "//llvm/lib/MC",
     "//llvm/lib/MC/MCDisassembler",
     "//llvm/lib/Object",