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authorDan Gohman <gohman@apple.com>2011-10-27 22:56:32 +0000
committerDan Gohman <gohman@apple.com>2011-10-27 22:56:32 +0000
commit4c9fca99c9a6734bb33c34aeaf40b71c4002757e (patch)
tree96ea6d2bd62f60abc91daa786209f84e58a41bc0 /llvm/utils
parentf211416dde4307d539c2f7ba18b36597e8f9b28a (diff)
downloadbcm5719-llvm-4c9fca99c9a6734bb33c34aeaf40b71c4002757e.tar.gz
bcm5719-llvm-4c9fca99c9a6734bb33c34aeaf40b71c4002757e.zip
Remove the Alpha backend.
llvm-svn: 143164
Diffstat (limited to 'llvm/utils')
-rw-r--r--llvm/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp2
-rw-r--r--llvm/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp2
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp b/llvm/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
index ac72b0872fe..0cbfc4b70f9 100644
--- a/llvm/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
+++ b/llvm/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
@@ -2,7 +2,7 @@
# Do not edit here. If you wish to override these values
# edit the last section
set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
set srcroot "/Volumes/Data/ddunbar/llvm"
set objroot "/Volumes/Data/ddunbar/llvm.obj.64"
set srcdir "/Volumes/Data/ddunbar/llvm/test"
diff --git a/llvm/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp b/llvm/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
index ac72b0872fe..0cbfc4b70f9 100644
--- a/llvm/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
+++ b/llvm/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
@@ -2,7 +2,7 @@
# Do not edit here. If you wish to override these values
# edit the last section
set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
set srcroot "/Volumes/Data/ddunbar/llvm"
set objroot "/Volumes/Data/ddunbar/llvm.obj.64"
set srcdir "/Volumes/Data/ddunbar/llvm/test"
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