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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2016-09-13 08:08:06 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2016-09-13 08:08:06 +0000 |
| commit | 05453991fecf42341312212d2c5c3f34f7f3f039 (patch) | |
| tree | 9a85783b3b669a1787b5694c698690ef62d217e3 /llvm/utils | |
| parent | b79f4d3970621b16a28202afb7c2e3c50256995d (diff) | |
| download | bcm5719-llvm-05453991fecf42341312212d2c5c3f34f7f3f039.tar.gz bcm5719-llvm-05453991fecf42341312212d2c5c3f34f7f3f039.zip | |
This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instruction
descriptions now tag add instructions, and the Hexagon backend is using this to
identify loop induction statements.
Patch by Sam Parker and Sjoerd Meijer.
Differential Revision: https://reviews.llvm.org/D23601
llvm-svn: 281304
Diffstat (limited to 'llvm/utils')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenInstruction.h | 1 | ||||
| -rw-r--r-- | llvm/utils/TableGen/InstrInfoEmitter.cpp | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/CodeGenInstruction.h b/llvm/utils/TableGen/CodeGenInstruction.h index 8e5a03d7b74..75db17b59ac 100644 --- a/llvm/utils/TableGen/CodeGenInstruction.h +++ b/llvm/utils/TableGen/CodeGenInstruction.h @@ -230,6 +230,7 @@ template <typename T> class ArrayRef; bool isSelect : 1; bool isBarrier : 1; bool isCall : 1; + bool isAdd : 1; bool canFoldAsLoad : 1; bool mayLoad : 1; bool mayLoad_Unset : 1; diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index 02461cc0508..e9c448d0445 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -482,6 +482,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)"; if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)"; if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)"; + if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)"; if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)"; if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)"; if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)"; |
