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| author | Craig Topper <craig.topper@intel.com> | 2018-08-03 06:12:56 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-08-03 06:12:56 +0000 |
| commit | e902b7d0b0f87489b52953ea83b92bf66039f452 (patch) | |
| tree | b2dbfdbd24662c1e37d81d167ec79846fbdd609d /llvm/utils/wciia.py | |
| parent | 58d837d347c4de12097843fa7579c02cf45c10d7 (diff) | |
| download | bcm5719-llvm-e902b7d0b0f87489b52953ea83b92bf66039f452.tar.gz bcm5719-llvm-e902b7d0b0f87489b52953ea83b92bf66039f452.zip | |
[X86] Support fp128 and/or/xor/load/store with VEX and EVEX encoded instructions.
Move all the patterns to X86InstrVecCompiler.td so we can keep SSE/AVX/AVX512 all in one place.
To save some patterns we'll use an existing DAG combine to convert f128 fand/for/fxor to integer when sse2 is enabled. This allows use to reuse all the existing patterns for v2i64.
I believe this now makes SHA instructions the only case where VEX/EVEX and legacy encoded instructions could be generated simultaneously.
llvm-svn: 338821
Diffstat (limited to 'llvm/utils/wciia.py')
0 files changed, 0 insertions, 0 deletions
