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authorCraig Topper <craig.topper@gmail.com>2015-12-29 07:03:23 +0000
committerCraig Topper <craig.topper@gmail.com>2015-12-29 07:03:23 +0000
commite4e74157056f177195464755c8733a3d2fee5b1f (patch)
treeb4a016e44d3ab6264e6fff1be9233670ed35368f /llvm/utils/TableGen
parent69773fb0d2cc275ef16f722b4f9c8188db3880f2 (diff)
downloadbcm5719-llvm-e4e74157056f177195464755c8733a3d2fee5b1f.tar.gz
bcm5719-llvm-e4e74157056f177195464755c8733a3d2fee5b1f.zip
[TableGen] Use range-based for loops. NFC
llvm-svn: 256539
Diffstat (limited to 'llvm/utils/TableGen')
-rw-r--r--llvm/utils/TableGen/AsmMatcherEmitter.cpp15
1 files changed, 5 insertions, 10 deletions
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index e55bbd37610..abbd7f13035 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -774,8 +774,7 @@ void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
// Find the ResOperand that refers to the operand we're aliasing away
// and update it to refer to the combined operand instead.
- for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
- ResOperand &Op = ResOperands[i];
+ for (ResOperand &Op : ResOperands) {
if (Op.Kind == ResOperand::RenderAsmOperand &&
Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
Op.AsmOperandNum = DstAsmOperand;
@@ -786,8 +785,7 @@ void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
// Adjust the ResOperand references to any AsmOperands that followed
// the one we just deleted.
- for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
- ResOperand &Op = ResOperands[i];
+ for (ResOperand &Op : ResOperands) {
switch(Op.Kind) {
default:
// Nothing to do for operands that don't reference AsmOperands.
@@ -1455,7 +1453,7 @@ void AsmMatcherInfo::buildInfo() {
StringRef Token = Op.Token;
// Check for singleton registers.
- if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
+ if (Record *RegRecord = Op.SingletonReg) {
Op.Class = RegisterClasses[RegRecord];
assert(Op.Class && Op.Class->Registers.size() == 1 &&
"Unexpected class for singleton register");
@@ -1515,8 +1513,7 @@ void AsmMatcherInfo::buildInfo() {
// information.
std::vector<Record*> AllTokenAliases =
Records.getAllDerivedDefinitions("TokenAlias");
- for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
- Record *Rec = AllTokenAliases[i];
+ for (Record *Rec : AllTokenAliases) {
ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
if (FromClass == ToClass)
@@ -1624,9 +1621,7 @@ void MatchableInfo::buildInstructionResultOperands() {
// Loop over all operands of the result instruction, determining how to
// populate them.
- for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
- const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
-
+ for (const CGIOperandList::OperandInfo &OpInfo : ResultInst->Operands) {
// If this is a tied operand, just copy from the previously handled operand.
int TiedOp = -1;
if (OpInfo.MINumOperands == 1)
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