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authorCraig Topper <craig.topper@gmail.com>2015-01-03 00:00:20 +0000
committerCraig Topper <craig.topper@gmail.com>2015-01-03 00:00:20 +0000
commitae8e1b3831502d49dd76fe96809876918552b3b4 (patch)
treedcc8f78ccbf082d91989ff32ed76b84d0bf8776f /llvm/utils/TableGen
parent017b830564b9f28bba4eee711f7b90227ea2496c (diff)
downloadbcm5719-llvm-ae8e1b3831502d49dd76fe96809876918552b3b4.tar.gz
bcm5719-llvm-ae8e1b3831502d49dd76fe96809876918552b3b4.zip
[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present.
llvm-svn: 225099
Diffstat (limited to 'llvm/utils/TableGen')
-rw-r--r--llvm/utils/TableGen/X86DisassemblerTables.cpp10
-rw-r--r--llvm/utils/TableGen/X86RecognizableInstr.cpp4
2 files changed, 12 insertions, 2 deletions
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 138a34b4dc9..fbe5502bc90 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -114,10 +114,12 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_64BIT_REXW:
return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
inheritsFrom(child, IC_64BIT_REXW_XD) ||
- inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
+ inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
+ (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE)));
case IC_64BIT_OPSIZE:
return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
- (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE));
+ (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE)) ||
+ (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE));
case IC_64BIT_XD:
return(inheritsFrom(child, IC_64BIT_REXW_XD));
case IC_64BIT_XS:
@@ -128,6 +130,7 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_64BIT_REXW_XD:
case IC_64BIT_REXW_XS:
case IC_64BIT_REXW_OPSIZE:
+ case IC_64BIT_REXW_ADSIZE:
return false;
case IC_VEX:
return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
@@ -720,6 +723,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
(index & ATTR_OPSIZE))
o << "IC_64BIT_REXW_OPSIZE";
+ else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
+ (index & ATTR_ADSIZE))
+ o << "IC_64BIT_REXW_ADSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
o << "IC_64BIT_XD_OPSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 91c64aa049e..56976d3ec38 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -408,6 +408,8 @@ InstructionContext RecognizableInstr::insnContext() const {
} else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
insnContext = IC_64BIT_REXW_OPSIZE;
+ else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
+ insnContext = IC_64BIT_REXW_ADSIZE;
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
insnContext = IC_64BIT_XD_OPSIZE;
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
@@ -984,6 +986,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("offset32_8", TYPE_MOFFS8)
TYPE("offset32_16", TYPE_MOFFS16)
TYPE("offset32_32", TYPE_MOFFS32)
+ TYPE("offset32_64", TYPE_MOFFS64)
TYPE("offset64_8", TYPE_MOFFS8)
TYPE("offset64_16", TYPE_MOFFS16)
TYPE("offset64_32", TYPE_MOFFS32)
@@ -1219,6 +1222,7 @@ RecognizableInstr::relocationEncodingFromString(const std::string &s,
ENCODING("offset32_8", ENCODING_Ia)
ENCODING("offset32_16", ENCODING_Ia)
ENCODING("offset32_32", ENCODING_Ia)
+ ENCODING("offset32_64", ENCODING_Ia)
ENCODING("offset64_8", ENCODING_Ia)
ENCODING("offset64_16", ENCODING_Ia)
ENCODING("offset64_32", ENCODING_Ia)
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