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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-28 21:01:46 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-28 21:01:46 +0000 |
| commit | 868af92235c9e871f952a1bca90a7b035b675a01 (patch) | |
| tree | 2ae7d319257ac0b82ed3d5a77674d4c797331aac /llvm/utils/TableGen | |
| parent | 9bb296cb05284fedf407dd1424bceb214991f5f2 (diff) | |
| download | bcm5719-llvm-868af92235c9e871f952a1bca90a7b035b675a01.tar.gz bcm5719-llvm-868af92235c9e871f952a1bca90a7b035b675a01.zip | |
TableGen: Add IntrHasSideEffects property for intrinsics
The IntrNoMem, IntrReadMem, IntrWriteMem, and IntrArgMemOnly intrinsic
properties differ from their corresponding LLVM IR attributes by specifying
that the intrinsic, in addition to its memory properties, has no other side
effects.
The IntrHasSideEffects flag used in combination with one of the memory flags
listed above, makes it possible to define an intrinsic such that its
properties at the CodeGen layer match its properties at the IR layer.
Patch by Tom Stellard
llvm-svn: 301685
Diffstat (limited to 'llvm/utils/TableGen')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 3 | ||||
| -rw-r--r-- | llvm/utils/TableGen/CodeGenIntrinsics.h | 4 | ||||
| -rw-r--r-- | llvm/utils/TableGen/CodeGenTarget.cpp | 3 | ||||
| -rw-r--r-- | llvm/utils/TableGen/IntrinsicEmitter.cpp | 3 |
4 files changed, 12 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp index 972eb9cd340..ef2cb4208ea 100644 --- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp @@ -2828,7 +2828,8 @@ public: if (IntInfo->ModRef & CodeGenIntrinsic::MR_Mod) mayStore = true;// Intrinsics that can write to memory are 'mayStore'. - if (IntInfo->ModRef >= CodeGenIntrinsic::ReadWriteMem) + if (IntInfo->ModRef >= CodeGenIntrinsic::ReadWriteMem || + IntInfo->hasSideEffects) // ReadWriteMem intrinsics can have other strange effects. hasSideEffects = true; } diff --git a/llvm/utils/TableGen/CodeGenIntrinsics.h b/llvm/utils/TableGen/CodeGenIntrinsics.h index d126f273a1a..24374127f53 100644 --- a/llvm/utils/TableGen/CodeGenIntrinsics.h +++ b/llvm/utils/TableGen/CodeGenIntrinsics.h @@ -123,6 +123,10 @@ struct CodeGenIntrinsic { /// True if the intrinsic is marked as convergent. bool isConvergent; + /// True if the intrinsic has side effects that aren't captured by any + /// of the other flags. + bool hasSideEffects; + // True if the intrinsic is marked as speculatable. bool isSpeculatable; diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp index aad9005de20..d1014a5668a 100644 --- a/llvm/utils/TableGen/CodeGenTarget.cpp +++ b/llvm/utils/TableGen/CodeGenTarget.cpp @@ -516,6 +516,7 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { isNoDuplicate = false; isConvergent = false; isSpeculatable = false; + hasSideEffects = false; if (DefName.size() <= 4 || std::string(DefName.begin(), DefName.begin() + 4) != "int_") @@ -656,6 +657,8 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { isNoReturn = true; else if (Property->getName() == "IntrSpeculatable") isSpeculatable = true; + else if (Property->getName() == "IntrHasSideEffects") + hasSideEffects = true; else if (Property->isSubClassOf("NoCapture")) { unsigned ArgNo = Property->getValueAsInt("ArgNo"); ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture)); diff --git a/llvm/utils/TableGen/IntrinsicEmitter.cpp b/llvm/utils/TableGen/IntrinsicEmitter.cpp index 72f2dce401e..1fc18a5dd1d 100644 --- a/llvm/utils/TableGen/IntrinsicEmitter.cpp +++ b/llvm/utils/TableGen/IntrinsicEmitter.cpp @@ -479,6 +479,9 @@ struct AttributeComparator { if (L->isSpeculatable != R->isSpeculatable) return R->isSpeculatable; + if (L->hasSideEffects != R->hasSideEffects) + return R->hasSideEffects; + // Try to order by readonly/readnone attribute. CodeGenIntrinsic::ModRefBehavior LK = L->ModRef; CodeGenIntrinsic::ModRefBehavior RK = R->ModRef; |

