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| author | Craig Topper <craig.topper@intel.com> | 2019-09-22 19:49:39 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-22 19:49:39 +0000 |
| commit | 80fda375b2250b51b3a547b0e2fe9cc7d99207d8 (patch) | |
| tree | a0a151a908d59f29fc395f9d9c4346ff064196ae /llvm/utils/TableGen | |
| parent | 24159592cac97442db50dd76da0a7cf191d04202 (diff) | |
| download | bcm5719-llvm-80fda375b2250b51b3a547b0e2fe9cc7d99207d8.tar.gz bcm5719-llvm-80fda375b2250b51b3a547b0e2fe9cc7d99207d8.zip | |
[X86][TableGen] Allow timm to appear in output patterns. Use it to remove ConvertToTarget opcodes from the X86 isel table.
We're now using a lot more TargetConstant nodes in SelectionDAG.
But we were still telling isel to convert some of them
to TargetConstants even though they already are. This is because
isel emits a conversion anytime the output pattern has a an 'imm'.
I guess for patterns in instructions we take the 'timm' from the
'set' pattern, but for Pat patterns with explcicit output we
previously had to say 'imm' since 'timm' wasn't allowed in outputs.
llvm-svn: 372525
Diffstat (limited to 'llvm/utils/TableGen')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp index ad1f228b9fa..46f986ca017 100644 --- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp @@ -2797,6 +2797,7 @@ TreePatternNodePtr TreePattern::ParseTreePattern(Init *TheInit, if (Operator->isSubClassOf("SDNode") && Operator->getName() != "imm" && + Operator->getName() != "timm" && Operator->getName() != "fpimm" && Operator->getName() != "tglobaltlsaddr" && Operator->getName() != "tconstpool" && |
