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| author | Javed Absar <javed.absar@arm.com> | 2017-03-27 20:46:37 +0000 |
|---|---|---|
| committer | Javed Absar <javed.absar@arm.com> | 2017-03-27 20:46:37 +0000 |
| commit | 3d594370933b515234c208a85a1c091d3e38d7f7 (patch) | |
| tree | 74e4b77190e8420c4d80ffe6096df575bc37525d /llvm/utils/TableGen | |
| parent | f1c2f2a668db86fc2143cfeeb3ff71579afabfbc (diff) | |
| download | bcm5719-llvm-3d594370933b515234c208a85a1c091d3e38d7f7.tar.gz bcm5719-llvm-3d594370933b515234c208a85a1c091d3e38d7f7.zip | |
Improve machine schedulers for in-order processors
This patch enables schedulers to specify instructions that
cannot be issued with any other instructions.
It also fixes BeginGroup/EndGroup.
Reviewed by: Andrew Trick
Differential Revision: https://reviews.llvm.org/D30744
llvm-svn: 298885
Diffstat (limited to 'llvm/utils/TableGen')
| -rw-r--r-- | llvm/utils/TableGen/SubtargetEmitter.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp index bf7b392b15e..30516ef5d10 100644 --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -917,6 +917,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps"); SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup"); SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup"); + SCDesc.BeginGroup |= WriteRes->getValueAsBit("SingleIssue"); + SCDesc.EndGroup |= WriteRes->getValueAsBit("SingleIssue"); // Create an entry for each ProcResource listed in WriteRes. RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources"); |
