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authorCraig Topper <craig.topper@intel.com>2018-06-13 00:04:08 +0000
committerCraig Topper <craig.topper@intel.com>2018-06-13 00:04:08 +0000
commit55488731be1b6df0a92683996ff2e34a06bae90b (patch)
treefaf822de2cd241a68accbceca75efcc2909c6667 /llvm/utils/TableGen/X86FoldTablesEmitter.cpp
parent4f9cac667ba4a50a6e8c46a3c5337751beaa3430 (diff)
downloadbcm5719-llvm-55488731be1b6df0a92683996ff2e34a06bae90b.tar.gz
bcm5719-llvm-55488731be1b6df0a92683996ff2e34a06bae90b.zip
[X86] Mark all instructions that have masked store semantics with NotMemoryFoldable. Remove dependency on SchedRW from memory table autogenerator.
Previously we were whitelisting in instructions based on their SchedRW value. With the masked store instructions explicitly removed via NotMemoryFoldable, we don't seem to need this check anymore. llvm-svn: 334563
Diffstat (limited to 'llvm/utils/TableGen/X86FoldTablesEmitter.cpp')
-rw-r--r--llvm/utils/TableGen/X86FoldTablesEmitter.cpp18
1 files changed, 2 insertions, 16 deletions
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index 190ad6caa31..5933c184d69 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -251,16 +251,6 @@ getMemOperandSize(const Record *MemRec, const bool IntrinsicSensitive = false) {
llvm_unreachable("Memory operand's size not known!");
}
-// Returns true if the record's list of defs includes the given def.
-static inline bool hasDefInList(const Record *Rec, const StringRef List,
- const StringRef Def) {
- if (!Rec->isValueUnset(List)) {
- return any_of(*(Rec->getValueAsListInit(List)),
- [Def](const Init *I) { return I->getAsString() == Def; });
- }
- return false;
-}
-
// Return true if the instruction defined as a register flavor.
static inline bool hasRegisterFormat(const Record *Inst) {
const BitsInit *FormBits = Inst->getValueAsBitsInit("FormBits");
@@ -515,12 +505,8 @@ void X86FoldTablesEmitter::updateTables(const CodeGenInstruction *RegInstr,
unsigned MemInSize = MemRec->getValueAsDag("InOperandList")->getNumArgs();
unsigned RegInSize = RegRec->getValueAsDag("InOperandList")->getNumArgs();
- // Instructions which have the WriteRMW value (Read-Modify-Write) should be
- // added to Table2Addr.
- if ((hasDefInList(MemRec, "SchedRW", "WriteRMW") ||
- hasDefInList(MemRec, "SchedRW", "WriteADCRMW") ||
- hasDefInList(MemRec, "SchedRW", "WriteALURMW")) &&
- MemOutSize != RegOutSize && MemInSize == RegInSize) {
+ // Instructions which Read-Modify-Write should be added to Table2Addr.
+ if (MemOutSize != RegOutSize && MemInSize == RegInSize) {
addEntryWithFlags(Table2Addr, RegInstr, MemInstr, S, 0);
return;
}
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