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authorCraig Topper <craig.topper@intel.com>2018-06-12 07:32:15 +0000
committerCraig Topper <craig.topper@intel.com>2018-06-12 07:32:15 +0000
commit51805de0928fcec6d88b80c73bba1160d369871b (patch)
tree3fccdc15502b5d7e95aa74b12f8297b9d22cf361 /llvm/utils/TableGen/X86FoldTablesEmitter.cpp
parenta9e7908e3066ef1d24970002108262cc46be3e5d (diff)
downloadbcm5719-llvm-51805de0928fcec6d88b80c73bba1160d369871b.tar.gz
bcm5719-llvm-51805de0928fcec6d88b80c73bba1160d369871b.zip
[X86] Update folding table generator to properly detect RMW arithmetic instructions.
The RMW instructions are detected by reading the SchedRW data, but the RMW instructions have had their SchedRW changed in recent months. This broke the expectation. We probably should fix this to use the mayLoad/mayStore flags if possible. llvm-svn: 334478
Diffstat (limited to 'llvm/utils/TableGen/X86FoldTablesEmitter.cpp')
-rw-r--r--llvm/utils/TableGen/X86FoldTablesEmitter.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index 1ebe9f9f8f0..6ef339b7a2f 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -517,8 +517,10 @@ void X86FoldTablesEmitter::updateTables(const CodeGenInstruction *RegInstr,
// Instructions which have the WriteRMW value (Read-Modify-Write) should be
// added to Table2Addr.
- if (hasDefInList(MemRec, "SchedRW", "WriteRMW") && MemOutSize != RegOutSize &&
- MemInSize == RegInSize) {
+ if ((hasDefInList(MemRec, "SchedRW", "WriteRMW") ||
+ hasDefInList(MemRec, "SchedRW", "WriteADCRMW") ||
+ hasDefInList(MemRec, "SchedRW", "WriteALURMW")) &&
+ MemOutSize != RegOutSize && MemInSize == RegInSize) {
addEntryWithFlags(Table2Addr, RegInstr, MemInstr, S, 0);
return;
}
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