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| author | Marina Yatsina <marina.yatsina@intel.com> | 2017-01-18 08:07:51 +0000 |
|---|---|---|
| committer | Marina Yatsina <marina.yatsina@intel.com> | 2017-01-18 08:07:51 +0000 |
| commit | 197db00e3ea7c6c5f2178e22ffb78061153203ff (patch) | |
| tree | 5e04b53d66e237ff600428326ba35b7848e47f13 /llvm/utils/TableGen/X86DisassemblerTables.cpp | |
| parent | 1301915aebdcd4f7897c81f0d6f867f014f05893 (diff) | |
| download | bcm5719-llvm-197db00e3ea7c6c5f2178e22ffb78061153203ff.tar.gz bcm5719-llvm-197db00e3ea7c6c5f2178e22ffb78061153203ff.zip | |
[X86] Fix for bugzilla 31576 - add support for "data32" instruction prefix
This patch fixes bugzilla 31576 (https://llvm.org/bugs/show_bug.cgi?id=31576).
"data32" instruction prefix was not defined in the llvm.
An exception had to be added to the X86 tablegen and AsmPrinter because both "data16" and "data32" are encoded to 0x66 (but in different modes).
Differential Revision: https://reviews.llvm.org/D28468
llvm-svn: 292352
Diffstat (limited to 'llvm/utils/TableGen/X86DisassemblerTables.cpp')
| -rw-r--r-- | llvm/utils/TableGen/X86DisassemblerTables.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index 5b710e44615..c9e36f96736 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -879,6 +879,10 @@ void DisassemblerTables::setTableFields(ModRMDecision &decision, newInfo.name == "XCHG64ar")) continue; // special case for XCHG*ar and NOOP + if (previousInfo.name == "DATA16_PREFIX" && + newInfo.name == "DATA32_PREFIX") + continue; // special case for data16 and data32 + if (outranks(previousInfo.insnContext, newInfo.insnContext)) continue; |
