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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-12-19 16:53:28 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-12-19 16:53:28 +0000 |
| commit | b92f557c4066e78d54eadca8bf1b8d304ce79c16 (patch) | |
| tree | 30e57e7ff0db218fa723536d2926c13c2ae6ff8b /llvm/utils/TableGen/X86DisassemblerShared.h | |
| parent | ba9cc6c1bbc258ccb93e3aab01eedd8d4df4f745 (diff) | |
| download | bcm5719-llvm-b92f557c4066e78d54eadca8bf1b8d304ce79c16.tar.gz bcm5719-llvm-b92f557c4066e78d54eadca8bf1b8d304ce79c16.zip | |
Synthesize register classes for TRI::getMatchingSuperRegClass().
Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results. The function is
still not auto-generated, so it still returns inexact results.
This produces these new register classes:
ARM:
QQPR_with_dsub_0_in_DPR_8
QQQQPR_with_dsub_0_in_DPR_8
X86:
GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
GR64_with_sub_16bit_in_GR16_NOREX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_with_sub_32bit_in_GR32_TC
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
GR64_with_sub_32bit_in_GR32_AD
GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX
The other targets in the tree are not weird enough to be affected.
llvm-svn: 146872
Diffstat (limited to 'llvm/utils/TableGen/X86DisassemblerShared.h')
0 files changed, 0 insertions, 0 deletions
