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| author | Evan Cheng <evan.cheng@apple.com> | 2006-05-01 09:14:40 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-05-01 09:14:40 +0000 |
| commit | 24e795496d2db0708602ba71fd7890f2e1cbfb91 (patch) | |
| tree | cdd6512de66616341a3f7eff6928a04635292ead /llvm/utils/TableGen/TableGenBackend.cpp | |
| parent | c2ef5e34a8141edf8096db2b2606cd9c120a065a (diff) | |
| download | bcm5719-llvm-24e795496d2db0708602ba71fd7890f2e1cbfb91.tar.gz bcm5719-llvm-24e795496d2db0708602ba71fd7890f2e1cbfb91.zip | |
Bottom up register-pressure reduction scheduler now pushes store operations
up the schedule. This helps code that looks like this:
loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...
Without this change, the stores and computations are more likely to
interleave:
loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...
This can increase the number of spills if we are unlucky.
llvm-svn: 28033
Diffstat (limited to 'llvm/utils/TableGen/TableGenBackend.cpp')
0 files changed, 0 insertions, 0 deletions
