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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-02-03 14:18:35 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-02-03 14:18:35 +0000 |
| commit | 320f79c8aa1066b0f46b84eb1564fcf705da5922 (patch) | |
| tree | 852e30f53ac0d08aff50efafa1d5463e5be99204 /llvm/utils/TableGen/TableGen.cpp | |
| parent | 4524268c02d076266ead0d05708ab4460a73ac0f (diff) | |
| download | bcm5719-llvm-320f79c8aa1066b0f46b84eb1564fcf705da5922.tar.gz bcm5719-llvm-320f79c8aa1066b0f46b84eb1564fcf705da5922.zip | |
[globalisel] Fix missing break.
The instruction selector has been emitting the register bank information too.
llvm-svn: 294007
Diffstat (limited to 'llvm/utils/TableGen/TableGen.cpp')
| -rw-r--r-- | llvm/utils/TableGen/TableGen.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp index c9a818e702a..6937f20b441 100644 --- a/llvm/utils/TableGen/TableGen.cpp +++ b/llvm/utils/TableGen/TableGen.cpp @@ -185,6 +185,7 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { break; case GenGlobalISel: EmitGlobalISel(Records, OS); + break; case GenRegisterBank: EmitRegisterBank(Records, OS); break; |
