Now generating instruction itineraries for scheduling. Not my best work, but...

llvm-svn: 24050

1 files changed, 21 insertions, 1 deletions

diff --git a/llvm/utils/TableGen/SubtargetEmitter.h b/llvm/utils/TableGen/SubtargetEmitter.h
index 7e2a7cb0a37..2a7b70be25d 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.h
+++ b/llvm/utils/TableGen/SubtargetEmitter.h
@@ -15,17 +15,37 @@
 #define SUBTARGET_EMITTER_H
 
 #include "TableGenBackend.h"
+#include "llvm/Target/TargetInstrItineraries.h"
+#include <vector>
+#include <map>
+#include <string>
+
 
 namespace llvm {
 
+//
+// Convenience types.
+//
+typedef std::map<std::string, unsigned> IntMap;
+typedef std::vector<InstrItinerary> IntineraryList;
+typedef std::vector<IntineraryList> ProcessorList;
+
 class SubtargetEmitter : public TableGenBackend {
+  
   RecordKeeper &Records;
   std::string Target;
   
   void Enumeration(std::ostream &OS, const char *ClassName, bool isBits);
   void FeatureKeyValues(std::ostream &OS);
   void CPUKeyValues(std::ostream &OS);
-  void SubtargetEmitter::ParseFeaturesFunction(std::ostream &OS);
+  unsigned CollectAllItinClasses(IntMap &ItinClassesMap);
+  void FormItineraryString(Record *ItinData, std::string &ItinString,
+                           unsigned &N);
+  void EmitStageData(std::ostream &OS, unsigned N,
+                     IntMap &ItinClassesMap, ProcessorList &ProcList);
+  void EmitProcessData(std::ostream &OS, ProcessorList &ProcList);
+  void EmitData(std::ostream &OS);
+  void ParseFeaturesFunction(std::ostream &OS);
   
 public:
   SubtargetEmitter(RecordKeeper &R) : Records(R) {}