summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/CodeGenTarget.cpp
diff options
context:
space:
mode:
authorJakob Stoklund Olesen <stoklund@2pi.dk>2011-04-20 18:19:48 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2011-04-20 18:19:48 +0000
commit0e34c1dfac5f55d58cf16197b3e87f49089a5339 (patch)
treed962d8b816d631b41da1bb3f6124d029ebda2d02 /llvm/utils/TableGen/CodeGenTarget.cpp
parentd828f316afaaf6825ea968eac5a46d34d375810d (diff)
downloadbcm5719-llvm-0e34c1dfac5f55d58cf16197b3e87f49089a5339.tar.gz
bcm5719-llvm-0e34c1dfac5f55d58cf16197b3e87f49089a5339.zip
Prefer cheap registers for busy live ranges.
On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
Diffstat (limited to 'llvm/utils/TableGen/CodeGenTarget.cpp')
-rw-r--r--llvm/utils/TableGen/CodeGenTarget.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index cc09c8d6833..c9ccb960d9f 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -172,6 +172,7 @@ void CodeGenTarget::ReadRegisters() const {
CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
DeclaredSpillSize = R->getValueAsInt("SpillSize");
DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
+ CostPerUse = R->getValueAsInt("CostPerUse");
}
const std::string &CodeGenRegister::getName() const {
OpenPOWER on IntegriCloud