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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-12-04 09:40:44 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-12-04 09:40:44 +0000 |
| commit | f1de34b84dea91b5060ee0fafbadaad5deaf199c (patch) | |
| tree | a9f9f3b64f43e764b76d989db0be6bbcd1e681fa /llvm/utils/TableGen/CodeGenSchedule.cpp | |
| parent | 8b24b32c44d77ca3121240a13e0f40cb6d5a766c (diff) | |
| download | bcm5719-llvm-f1de34b84dea91b5060ee0fafbadaad5deaf199c.tar.gz bcm5719-llvm-f1de34b84dea91b5060ee0fafbadaad5deaf199c.zip | |
Masked Load / Store Intrinsics - the CodeGen part.
I'm recommiting the codegen part of the patch.
The vectorizer part will be send to review again.
Masked Vector Load and Store Intrinsics.
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.
Added SDNodes for masked operations and lowering patterns for X86 code generator.
Examples:
<16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask)
declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask)
Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.
http://reviews.llvm.org/D6191
llvm-svn: 223348
Diffstat (limited to 'llvm/utils/TableGen/CodeGenSchedule.cpp')
0 files changed, 0 insertions, 0 deletions
