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| author | Owen Anderson <resistor@mac.com> | 2015-01-31 07:49:41 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2015-01-31 07:49:41 +0000 |
| commit | a366d7b217f67effd4b56a6af7cb82f84d1242cb (patch) | |
| tree | d5d1793dfc61c441dab3dd65a9c27844d594eeaa /llvm/utils/TableGen/CodeGenRegisters.h | |
| parent | 30526e79e87f7875a3f9652e4cdfa5a8ca51b701 (diff) | |
| download | bcm5719-llvm-a366d7b217f67effd4b56a6af7cb82f84d1242cb.tar.gz bcm5719-llvm-a366d7b217f67effd4b56a6af7cb82f84d1242cb.zip | |
Change more of the guts of CodeGenRegister's RegUnit tracking to be based on bit vectors.
This is a continuation of my prior work to move some of the inner workings for CodeGenRegister to use bit vectors when computing about register units. This is highly beneficial to TableGen runtime on targets with large, dense register files. This patch represents a ~40% runtime reduction over and above my earlier improvement on a stress test of this case.
llvm-svn: 227678
Diffstat (limited to 'llvm/utils/TableGen/CodeGenRegisters.h')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenRegisters.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h index 87a0dcf7af3..3fbf6e162c4 100644 --- a/llvm/utils/TableGen/CodeGenRegisters.h +++ b/llvm/utils/TableGen/CodeGenRegisters.h @@ -19,6 +19,7 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SparseBitVector.h" #include "llvm/CodeGen/MachineValueType.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/TableGen/Record.h" @@ -197,23 +198,23 @@ namespace llvm { } // List of register units in ascending order. - typedef SmallVector<unsigned, 16> RegUnitList; + typedef SparseBitVector<> RegUnitList; typedef SmallVector<unsigned, 16> RegUnitLaneMaskList; // How many entries in RegUnitList are native? - unsigned NumNativeRegUnits; + RegUnitList NativeRegUnits; // Get the list of register units. // This is only valid after computeSubRegs() completes. const RegUnitList &getRegUnits() const { return RegUnits; } ArrayRef<unsigned> getRegUnitLaneMasks() const { - return makeArrayRef(RegUnitLaneMasks).slice(0, NumNativeRegUnits); + return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count()); } // Get the native register units. This is a prefix of getRegUnits(). - ArrayRef<unsigned> getNativeRegUnits() const { - return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits); + RegUnitList getNativeRegUnits() const { + return NativeRegUnits; } void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) { @@ -225,8 +226,8 @@ namespace llvm { bool inheritRegUnits(CodeGenRegBank &RegBank); // Adopt a register unit for pressure tracking. - // A unit is adopted iff its unit number is >= NumNativeRegUnits. - void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); } + // A unit is adopted iff its unit number is >= NativeRegUnits.count(). + void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); } // Get the sum of this register's register unit weights. unsigned getWeight(const CodeGenRegBank &RegBank) const; |

