Stop inferring isVariadic from instruction patterns.

Instructions are now only marked as variadic if they use variable_ops in
their ins list.

A variadic SDNode is typically used for call nodes that have the call
arguments as operands.

A variadic MachineInstr can actually encode a variable number of
operands, for example ARM's stm/ldm instructions. A call instruction
does not have to be variadic. The call argument registers are added as
implicit operands.

This change remove the MCID::Variadic flags from most call and return
instructions, allowing us to better verify their operands.

llvm-svn: 162599

1 files changed, 5 insertions, 1 deletions

diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
index 2e4ec67d545..7512ae8a25e 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -2502,7 +2502,11 @@ static bool InferFromPattern(CodeGenInstruction &InstInfo,
 
   // These flags are silently added without any verification.
   InstInfo.isBitcast |= PatInfo.isBitcast;
-  InstInfo.Operands.isVariadic |= PatInfo.isVariadic;
+
+  // Don't infer isVariadic. This flag means something different on SDNodes and
+  // instructions. For example, a CALL SDNode is variadic because it has the
+  // call arguments as operands, but a CALL instruction is not variadic - it
+  // has argument registers as implicit, not explicit uses.
 
   return Error;
 }