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authorChris Lattner <sabre@nondot.org>2009-09-13 20:08:00 +0000
committerChris Lattner <sabre@nondot.org>2009-09-13 20:08:00 +0000
commit06c5eed9e9630037e6e5b20c4f99354232d1c8f8 (patch)
tree165641358f2c543008c4f87d8a968809bd809fc4 /llvm/utils/TableGen/AsmWriterEmitter.cpp
parent6822e695c1f932477f22410f66eb8bd2d84fb81f (diff)
downloadbcm5719-llvm-06c5eed9e9630037e6e5b20c4f99354232d1c8f8.tar.gz
bcm5719-llvm-06c5eed9e9630037e6e5b20c4f99354232d1c8f8.zip
make tblgen produce a function that returns the name for a physreg.
Nothing is using this info yet. llvm-svn: 81707
Diffstat (limited to 'llvm/utils/TableGen/AsmWriterEmitter.cpp')
-rw-r--r--llvm/utils/TableGen/AsmWriterEmitter.cpp54
1 files changed, 46 insertions, 8 deletions
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index a6f614958be..0455c9b5e81 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -538,19 +538,16 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
}
-
-void AsmWriterEmitter::run(raw_ostream &O) {
- EmitSourceFileHeader("Assembly Writer Source Fragment", O);
-
+/// EmitPrintInstruction - Generate the code for the "printInstruction" method
+/// implementation.
+void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
CodeGenTarget Target;
Record *AsmWriter = Target.getAsmWriter();
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
-
+
O <<
"/// printInstruction - This method is automatically generated by tablegen\n"
- "/// from the instruction set description. This method returns true if the\n"
- "/// machine instruction was sufficiently described to print it, otherwise\n"
- "/// it returns false.\n"
+ "/// from the instruction set description.\n"
"void " << Target.getName() << ClassName
<< "::printInstruction(const MachineInstr *MI) {\n";
@@ -794,3 +791,44 @@ void AsmWriterEmitter::run(raw_ostream &O) {
O << " return;\n";
O << "}\n";
}
+
+
+void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
+ CodeGenTarget Target;
+ Record *AsmWriter = Target.getAsmWriter();
+ std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
+ const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
+
+ O <<
+ "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
+ "/// from the register set description. This returns the assembler name\n"
+ "/// for the specified register.\n"
+ "const char *" << Target.getName() << ClassName
+ << "::getRegisterName(unsigned RegNo) const {\n"
+ << " assert(RegNo && RegNo < " << (Registers.size()+1)
+ << " && \"Invalid register number!\");\n"
+ << "\n"
+ << " static const char *const RegAsmNames[] = {\n";
+ for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
+ const CodeGenRegister &Reg = Registers[i];
+
+ std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
+ if (AsmName.empty())
+ AsmName = Reg.getName();
+ O << " \"" << AsmName << "\",\n";
+ }
+ O << " 0\n"
+ << " };\n"
+ << "\n"
+ << " return RegAsmNames[RegNo-1];\n"
+ << "}\n";
+}
+
+
+void AsmWriterEmitter::run(raw_ostream &O) {
+ EmitSourceFileHeader("Assembly Writer Source Fragment", O);
+
+ EmitPrintInstruction(O);
+ EmitGetRegisterName(O);
+}
+
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