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| author | Clement Courbet <courbet@google.com> | 2018-06-01 14:18:02 +0000 | 
|---|---|---|
| committer | Clement Courbet <courbet@google.com> | 2018-06-01 14:18:02 +0000 | 
| commit | df79e79e225c05d1b4e6fce51d17b038e1caf863 (patch) | |
| tree | 988fd0e43d69e0e2514e00c471ba5722b6921f47 /llvm/unittests | |
| parent | d101b5d7f7b82da622af6574d9fb5764c8c6cb1c (diff) | |
| download | bcm5719-llvm-df79e79e225c05d1b4e6fce51d17b038e1caf863.tar.gz bcm5719-llvm-df79e79e225c05d1b4e6fce51d17b038e1caf863.zip  | |
[llvm-exegesis] Analysis: Display idealized sched class port pressure.
Summary: Screenshot in phabricator diff.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D47329
llvm-svn: 333753
Diffstat (limited to 'llvm/unittests')
| -rw-r--r-- | llvm/unittests/tools/llvm-exegesis/X86/AnalysisTest.cpp | 102 | ||||
| -rw-r--r-- | llvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt | 1 | 
2 files changed, 103 insertions, 0 deletions
diff --git a/llvm/unittests/tools/llvm-exegesis/X86/AnalysisTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/AnalysisTest.cpp new file mode 100644 index 00000000000..d2d4c152d79 --- /dev/null +++ b/llvm/unittests/tools/llvm-exegesis/X86/AnalysisTest.cpp @@ -0,0 +1,102 @@ +#include "Analysis.h" + +#include <cassert> +#include <memory> + +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "gmock/gmock.h" +#include "gtest/gtest.h" + +namespace exegesis { +namespace { + +using testing::Pair; +using testing::UnorderedElementsAre; + +class AnalysisTest : public ::testing::Test { +protected: +  AnalysisTest() { +    const std::string TT = "x86_64-unknown-linux"; +    std::string error; +    const llvm::Target *const TheTarget = +        llvm::TargetRegistry::lookupTarget(TT, error); +    if (!TheTarget) { +      llvm::errs() << error << "\n"; +      return; +    } +    STI.reset(TheTarget->createMCSubtargetInfo(TT, "haswell", "")); + +    // Compute the ProxResIdx of ports unes in tests. +    const auto &SM = STI->getSchedModel(); +    for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) { +      const std::string Name = SM.getProcResource(I)->Name; +      if (Name == "HWPort0") { +        P0Idx = I; +      } else if (Name == "HWPort1") { +        P1Idx = I; +      } else if (Name == "HWPort5") { +        P5Idx = I; +      } else if (Name == "HWPort6") { +        P6Idx = I; +      } else if (Name == "HWPort05") { +        P05Idx = I; +      } else if (Name == "HWPort0156") { +        P0156Idx = I; +      } +    } +    EXPECT_NE(P0Idx, 0); +    EXPECT_NE(P1Idx, 0); +    EXPECT_NE(P5Idx, 0); +    EXPECT_NE(P6Idx, 0); +    EXPECT_NE(P05Idx, 0); +    EXPECT_NE(P0156Idx, 0); +  } + +  static void SetUpTestCase() { +    LLVMInitializeX86TargetInfo(); +    LLVMInitializeX86Target(); +    LLVMInitializeX86TargetMC(); +  } + +protected: +  std::unique_ptr<const llvm::MCSubtargetInfo> STI; +  uint16_t P0Idx = 0; +  uint16_t P1Idx = 0; +  uint16_t P5Idx = 0; +  uint16_t P6Idx = 0; +  uint16_t P05Idx = 0; +  uint16_t P0156Idx = 0; +}; + +TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_2P0) { +  const auto Pressure = +      computeIdealizedProcResPressure(STI->getSchedModel(), {{P0Idx, 2}}); +  EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(P0Idx, 2.0))); +} + +TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_2P05) { +  const auto Pressure = +      computeIdealizedProcResPressure(STI->getSchedModel(), {{P05Idx, 2}}); +  EXPECT_THAT(Pressure, +              UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P5Idx, 1.0))); +} + +TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_2P05_2P0156) { +  const auto Pressure = computeIdealizedProcResPressure( +      STI->getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}}); +  EXPECT_THAT(Pressure, +              UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0), +                                   Pair(P5Idx, 1.0), Pair(P6Idx, 1.0))); +} + +TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_1P1_1P05_2P0156) { +  const auto Pressure = computeIdealizedProcResPressure( +      STI->getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}}); +  EXPECT_THAT(Pressure, +              UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0), +                                   Pair(P5Idx, 1.0), Pair(P6Idx, 1.0))); +} + +} // namespace +} // namespace exegesis diff --git a/llvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt b/llvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt index e8b1381d8ba..b4e5ff6ef97 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt +++ b/llvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt @@ -16,5 +16,6 @@ set(LLVM_LINK_COMPONENTS  add_llvm_unittest(LLVMExegesisX86Tests    RegisterAliasingTest.cpp    AssemblerTest.cpp +  AnalysisTest.cpp    )  target_link_libraries(LLVMExegesisX86Tests PRIVATE LLVMExegesis)  | 

