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authorSimon Atanasyan <simon@atanasyan.com>2019-10-11 20:26:08 +0000
committerSimon Atanasyan <simon@atanasyan.com>2019-10-11 20:26:08 +0000
commitcf1ba238d4f752133897af1773e85056b1492803 (patch)
tree72ae269f59cdc31ded2bfea67cd28e756f198541 /llvm/unittests/tools
parent9c36ec5941730364d4b9befd15e20365a039a2f1 (diff)
downloadbcm5719-llvm-cf1ba238d4f752133897af1773e85056b1492803.tar.gz
bcm5719-llvm-cf1ba238d4f752133897af1773e85056b1492803.zip
[Mips][llvm-exegesis] Add a Mips target
The target does just enough to be able to run llvm-exegesis in latency mode for at least some opcodes. Patch by Miloš Stojanović. Differential Revision: https://reviews.llvm.org/D68649 llvm-svn: 374590
Diffstat (limited to 'llvm/unittests/tools')
-rw-r--r--llvm/unittests/tools/llvm-exegesis/CMakeLists.txt3
-rw-r--r--llvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt21
-rw-r--r--llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp91
3 files changed, 115 insertions, 0 deletions
diff --git a/llvm/unittests/tools/llvm-exegesis/CMakeLists.txt b/llvm/unittests/tools/llvm-exegesis/CMakeLists.txt
index 05b2b3bc605..d6d2a2d743c 100644
--- a/llvm/unittests/tools/llvm-exegesis/CMakeLists.txt
+++ b/llvm/unittests/tools/llvm-exegesis/CMakeLists.txt
@@ -30,3 +30,6 @@ endif()
if(LLVM_TARGETS_TO_BUILD MATCHES "PowerPC")
add_subdirectory(PowerPC)
endif()
+if(LLVM_TARGETS_TO_BUILD MATCHES "Mips")
+ add_subdirectory(Mips)
+endif()
diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt b/llvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt
new file mode 100644
index 00000000000..d6955d34706
--- /dev/null
+++ b/llvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt
@@ -0,0 +1,21 @@
+include_directories(
+ ${LLVM_MAIN_SRC_DIR}/lib/Target/Mips
+ ${LLVM_BINARY_DIR}/lib/Target/Mips
+ ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
+ )
+
+set(LLVM_LINK_COMPONENTS
+ MC
+ MCParser
+ Object
+ Support
+ Symbolize
+ Mips
+ )
+
+add_llvm_unittest(LLVMExegesisMipsTests
+ TargetTest.cpp
+ )
+target_link_libraries(LLVMExegesisMipsTests PRIVATE
+ LLVMExegesis
+ LLVMExegesisMips)
diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp
new file mode 100644
index 00000000000..16c8e5fda27
--- /dev/null
+++ b/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp
@@ -0,0 +1,91 @@
+//===-- TargetTest.cpp ------------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "Target.h"
+
+#include <cassert>
+#include <memory>
+
+#include "MCTargetDesc/MipsMCTargetDesc.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "gmock/gmock.h"
+#include "gtest/gtest.h"
+
+namespace llvm {
+namespace exegesis {
+
+void InitializeMipsExegesisTarget();
+
+namespace {
+
+using testing::AllOf;
+using testing::ElementsAre;
+using testing::Eq;
+using testing::Matcher;
+using testing::Property;
+
+Matcher<MCOperand> IsImm(int64_t Value) {
+ return AllOf(Property(&MCOperand::isImm, Eq(true)),
+ Property(&MCOperand::getImm, Eq(Value)));
+}
+
+Matcher<MCOperand> IsReg(unsigned Reg) {
+ return AllOf(Property(&MCOperand::isReg, Eq(true)),
+ Property(&MCOperand::getReg, Eq(Reg)));
+}
+
+Matcher<MCInst> OpcodeIs(unsigned Opcode) {
+ return Property(&MCInst::getOpcode, Eq(Opcode));
+}
+
+Matcher<MCInst> IsLoadLowImm(int64_t Reg, int64_t Value) {
+ return AllOf(OpcodeIs(Mips::ORi),
+ ElementsAre(IsReg(Reg), IsReg(Mips::ZERO), IsImm(Value)));
+}
+
+constexpr const char kTriple[] = "mips-unknown-linux";
+
+class MipsTargetTest : public ::testing::Test {
+protected:
+ MipsTargetTest() : State(kTriple, "mips32", "") {}
+
+ static void SetUpTestCase() {
+ LLVMInitializeMipsTargetInfo();
+ LLVMInitializeMipsTarget();
+ LLVMInitializeMipsTargetMC();
+ InitializeMipsExegesisTarget();
+ }
+
+ std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
+ return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,
+ Value);
+ }
+
+ LLVMState State;
+};
+
+TEST_F(MipsTargetTest, SetRegToConstant) {
+ const uint16_t Value = 0xFFFFU;
+ const unsigned Reg = Mips::T0;
+ EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
+ ElementsAre(IsLoadLowImm(Reg, Value)));
+}
+
+TEST_F(MipsTargetTest, DefaultPfmCounters) {
+ const std::string Expected = "CYCLES";
+ EXPECT_EQ(State.getExegesisTarget().getPfmCounters("").CycleCounter,
+ Expected);
+ EXPECT_EQ(
+ State.getExegesisTarget().getPfmCounters("unknown_cpu").CycleCounter,
+ Expected);
+}
+
+} // namespace
+} // namespace exegesis
+} // namespace llvm
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