summaryrefslogtreecommitdiffstats
path: root/llvm/unittests/Target
diff options
context:
space:
mode:
authorSam Parker <sam.parker@arm.com>2020-01-10 13:08:30 +0000
committerSam Parker <sam.parker@arm.com>2020-01-10 14:24:25 +0000
commit3772ea9dd9368cfdc73595854c143bc3f16a5ade (patch)
tree9fc551cae83473c47fe751bfe88d61df9175af33 /llvm/unittests/Target
parent2f2f41e12c5201b600d887d22ce5cb4afd2ff594 (diff)
downloadbcm5719-llvm-3772ea9dd9368cfdc73595854c143bc3f16a5ade.tar.gz
bcm5719-llvm-3772ea9dd9368cfdc73595854c143bc3f16a5ade.zip
[ARM][MVE] Tail predicate VMAX,VMAXA,VMIN,VMINA
Add the MVE min and max instructions to our tail predication whitelist. Differential Revision: https://reviews.llvm.org/D72502
Diffstat (limited to 'llvm/unittests/Target')
-rw-r--r--llvm/unittests/Target/ARM/MachineInstrTest.cpp18
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
index 581d8be2652..f5b7414deca 100644
--- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp
+++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -149,6 +149,24 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
case MVE_VFMA_qr_Sf32:
case MVE_VFMA_qr_f16:
case MVE_VFMA_qr_f32:
+ case MVE_VMAXAs16:
+ case MVE_VMAXAs32:
+ case MVE_VMAXAs8:
+ case MVE_VMAXs16:
+ case MVE_VMAXs32:
+ case MVE_VMAXs8:
+ case MVE_VMAXu16:
+ case MVE_VMAXu32:
+ case MVE_VMAXu8:
+ case MVE_VMINAs16:
+ case MVE_VMINAs32:
+ case MVE_VMINAs8:
+ case MVE_VMINs16:
+ case MVE_VMINs32:
+ case MVE_VMINs8:
+ case MVE_VMINu16:
+ case MVE_VMINu32:
+ case MVE_VMINu8:
case MVE_VMLAS_qr_s16:
case MVE_VMLAS_qr_s32:
case MVE_VMLAS_qr_s8:
OpenPOWER on IntegriCloud