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| author | Sam Parker <sam.parker@arm.com> | 2019-12-13 14:41:08 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2019-12-20 08:33:01 +0000 |
| commit | 4f0fe6b97e4463d5c8571ac71b23c63387251444 (patch) | |
| tree | 802f89be9f199c7716d1f3244fa068459607b87e /llvm/unittests/Target/ARM/MachineInstrTest.cpp | |
| parent | e8efac4b15303932581c128dc3976f4359388338 (diff) | |
| download | bcm5719-llvm-4f0fe6b97e4463d5c8571ac71b23c63387251444.tar.gz bcm5719-llvm-4f0fe6b97e4463d5c8571ac71b23c63387251444.zip | |
[ARM][MVE] Tail predicate bottom/top muls.
Add VMULL and VQDMULL variants to our tail predication white list.
Differential Revision: https://reviews.llvm.org/D71465
Diffstat (limited to 'llvm/unittests/Target/ARM/MachineInstrTest.cpp')
| -rw-r--r-- | llvm/unittests/Target/ARM/MachineInstrTest.cpp | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp index 8807a2f3182..581d8be2652 100644 --- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp +++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp @@ -15,7 +15,6 @@ using namespace llvm; // descriptions. Currently we, conservatively, disallow: // - cross beat carries. // - narrowing of results. -// - top/bottom operations. // - complex operations. // - horizontal operations. // - byte swapping. @@ -243,6 +242,22 @@ TEST(MachineInstrValidTailPredication, IsCorrect) { case MVE_VMOVimmi32: case MVE_VMOVimmi64: case MVE_VMOVimmi8: + case MVE_VMULLBp16: + case MVE_VMULLBp8: + case MVE_VMULLBs16: + case MVE_VMULLBs32: + case MVE_VMULLBs8: + case MVE_VMULLBu16: + case MVE_VMULLBu32: + case MVE_VMULLBu8: + case MVE_VMULLTp16: + case MVE_VMULLTp8: + case MVE_VMULLTs16: + case MVE_VMULLTs32: + case MVE_VMULLTs8: + case MVE_VMULLTu16: + case MVE_VMULLTu32: + case MVE_VMULLTu8: case MVE_VMUL_qr_f16: case MVE_VMUL_qr_f32: case MVE_VMUL_qr_i16: @@ -287,6 +302,14 @@ TEST(MachineInstrValidTailPredication, IsCorrect) { case MVE_VQADDu16: case MVE_VQADDu32: case MVE_VQADDu8: + case MVE_VQDMULL_qr_s16bh: + case MVE_VQDMULL_qr_s16th: + case MVE_VQDMULL_qr_s32bh: + case MVE_VQDMULL_qr_s32th: + case MVE_VQDMULLs16bh: + case MVE_VQDMULLs16th: + case MVE_VQDMULLs32bh: + case MVE_VQDMULLs32th: case MVE_VQNEGs16: case MVE_VQNEGs32: case MVE_VQNEGs8: |
