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| author | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-05-13 10:10:24 +0000 |
|---|---|---|
| committer | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-05-13 10:10:24 +0000 |
| commit | 6dcef8fc0c671002c017374b48b09be08bf516f1 (patch) | |
| tree | 9eaeb4ac5fac258e5c9c9364fc315090047aa454 /llvm/unittests/Support | |
| parent | 3c72fe1bad4a5a461e7f92fb0d90fb5876cbab81 (diff) | |
| download | bcm5719-llvm-6dcef8fc0c671002c017374b48b09be08bf516f1.tar.gz bcm5719-llvm-6dcef8fc0c671002c017374b48b09be08bf516f1.zip | |
[AArch64][SVE2] Add SVE2 target features to backend and TargetParser
Summary:
This patch adds the following features defined by Arm SVE2 architecture
extension:
sve2, sve2-aes, sve2-sm4, sve2-sha3, bitperm
For existing CPUs these features are declared as unsupported to prevent
scheduler errors.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewers: SjoerdMeijer, sdesmalen, ostannard, rovka
Reviewed By: SjoerdMeijer, rovka
Subscribers: rovka, javed.absar, tschuett, kristof.beyls, kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61513
llvm-svn: 360573
Diffstat (limited to 'llvm/unittests/Support')
| -rw-r--r-- | llvm/unittests/Support/TargetParserTest.cpp | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp index 420ec709ca6..a973d980d26 100644 --- a/llvm/unittests/Support/TargetParserTest.cpp +++ b/llvm/unittests/Support/TargetParserTest.cpp @@ -1014,8 +1014,8 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { AArch64::AEK_FP16 | AArch64::AEK_PROFILE | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_SVE | - AArch64::AEK_DOTPROD | AArch64::AEK_RCPC | - AArch64::AEK_FP16FML; + AArch64::AEK_SVE2 | AArch64::AEK_DOTPROD | + AArch64::AEK_RCPC | AArch64::AEK_FP16FML; for (unsigned i = 0; i <= Extensions; i++) EXPECT_TRUE(i == 0 ? !AArch64::getExtensionFeatures(i, Features) @@ -1043,6 +1043,14 @@ TEST(TargetParserTest, AArch64ArchExtFeature) { {"lse", "nolse", "+lse", "-lse"}, {"rdm", "nordm", "+rdm", "-rdm"}, {"sve", "nosve", "+sve", "-sve"}, + {"sve2", "nosve2", "+sve2", "-sve2"}, + {"sve2-aes", "nosve2-aes", "+sve2-aes", + "-sve2-aes"}, + {"sve2-sm4", "nosve2-sm4", "+sve2-sm4", + "-sve2-sm4"}, + {"sve2-sha3", "nosve2-sha3", "+sve2-sha3", + "-sve2-sha3"}, + {"bitperm", "nobitperm", "+bitperm", "-bitperm"}, {"dotprod", "nodotprod", "+dotprod", "-dotprod"}, {"rcpc", "norcpc", "+rcpc", "-rcpc" }, {"rng", "norng", "+rand", "-rand"}, |
