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authorJaved Absar <javed.absar@arm.com>2016-10-07 12:06:40 +0000
committerJaved Absar <javed.absar@arm.com>2016-10-07 12:06:40 +0000
commitfb4b6e8db988a620b692cd502687c738024362b5 (patch)
tree413c16d8285f4762b26ee20994c5a0c44227449a /llvm/unittests/Support/TargetParserTest.cpp
parentf03039fb4de75833d6e1accf9e0622d0b3bcd6e6 (diff)
downloadbcm5719-llvm-fb4b6e8db988a620b692cd502687c738024362b5.tar.gz
bcm5719-llvm-fb4b6e8db988a620b692cd502687c738024362b5.zip
[ARM]: Add Cortex-R52 target to LLVM
This patch adds Cortex-R52, the new ARM real-time processor, to LLVM. Cortex-R52 implements the ARMv8-R architecture. llvm-svn: 283542
Diffstat (limited to 'llvm/unittests/Support/TargetParserTest.cpp')
-rw-r--r--llvm/unittests/Support/TargetParserTest.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp
index ae1dacd3a06..183bf1d3da0 100644
--- a/llvm/unittests/Support/TargetParserTest.cpp
+++ b/llvm/unittests/Support/TargetParserTest.cpp
@@ -318,7 +318,7 @@ TEST(TargetParserTest, ARMparseCPUArch) {
"cortex-m3", "cortex-m4", "cortex-m7", "cortex-a32",
"cortex-a35", "cortex-a53", "cortex-a57", "cortex-a72",
"cortex-a73", "cyclone", "exynos-m1", "exynos-m2",
- "iwmmxt", "xscale", "swift"};
+ "iwmmxt", "xscale", "swift", "cortex-r52"};
for (const auto &ARMCPUName : kARMCPUNames) {
if (contains(CPU, ARMCPUName.Name))
@@ -335,7 +335,7 @@ TEST(TargetParserTest, ARMparseArchEndianAndISA) {
"v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a",
"v7", "v7a", "v7hl", "v7l", "v7-r", "v7r", "v7-m", "v7m",
"v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a", "v8.1-a",
- "v8.1a", "v8.2-a", "v8.2a"};
+ "v8.1a", "v8.2-a", "v8.2a", "v8-r"};
for (unsigned i = 0; i < array_lengthof(Arch); i++) {
std::string arm_1 = "armeb" + (std::string)(Arch[i]);
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