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| author | George Burgess IV <george.burgess.iv@gmail.com> | 2017-02-09 23:29:14 +0000 |
|---|---|---|
| committer | George Burgess IV <george.burgess.iv@gmail.com> | 2017-02-09 23:29:14 +0000 |
| commit | ccf11c2f9f8182943ba72352d5d19be989f816b1 (patch) | |
| tree | 596d8215edfcd54ab0fc360f47fd5ae977811f24 /llvm/unittests/Support/TargetParserTest.cpp | |
| parent | d57282791d912f18cf363a324a1c8a5c72814152 (diff) | |
| download | bcm5719-llvm-ccf11c2f9f8182943ba72352d5d19be989f816b1.tar.gz bcm5719-llvm-ccf11c2f9f8182943ba72352d5d19be989f816b1.zip | |
[ARM] Add support for armv7ve triple in llvm (PR31358).
Gcc supports target armv7ve which is armv7-a with virtualization
extensions. This change adds support for this in llvm for gcc
compatibility.
Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models as
this is specified automatically by FeatureVirtualization.
Patch by Manoj Gupta.
Differential Revision: https://reviews.llvm.org/D29472
llvm-svn: 294661
Diffstat (limited to 'llvm/unittests/Support/TargetParserTest.cpp')
| -rw-r--r-- | llvm/unittests/Support/TargetParserTest.cpp | 38 |
1 files changed, 21 insertions, 17 deletions
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp index 01136cb9717..aaaf1fd95f6 100644 --- a/llvm/unittests/Support/TargetParserTest.cpp +++ b/llvm/unittests/Support/TargetParserTest.cpp @@ -17,17 +17,17 @@ using namespace llvm; namespace { const char *ARMArch[] = { - "armv2", "armv2a", "armv3", "armv3m", "armv4", - "armv4t", "armv5", "armv5t", "armv5e", "armv5te", - "armv5tej", "armv6", "armv6j", "armv6k", "armv6hl", - "armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m", - "armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7", - "armv7a", "armv7hl", "armv7l", "armv7-r", "armv7r", - "armv7-m", "armv7m", "armv7k", "armv7s", "armv7e-m", - "armv7em", "armv8-a", "armv8", "armv8a", "armv8.1-a", - "armv8.1a", "armv8.2-a", "armv8.2a", "armv8-r", "armv8r", - "armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt", - "iwmmxt2", "xscale"}; + "armv2", "armv2a", "armv3", "armv3m", "armv4", + "armv4t", "armv5", "armv5t", "armv5e", "armv5te", + "armv5tej", "armv6", "armv6j", "armv6k", "armv6hl", + "armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m", + "armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7", + "armv7a", "armv7ve", "armv7hl", "armv7l", "armv7-r", + "armv7r", "armv7-m", "armv7m", "armv7k", "armv7s", + "armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a", + "armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a", "armv8-r", + "armv8r", "armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main", + "iwmmxt", "iwmmxt2", "xscale"}; bool testARMCPU(StringRef CPUName, StringRef ExpectedArch, StringRef ExpectedFPU, unsigned ExpectedFlags, @@ -315,6 +315,9 @@ TEST(TargetParserTest, testARMArch) { testARMArch("armv7-a", "cortex-a8", "v7", ARMBuildAttrs::CPUArch::v7)); EXPECT_TRUE( + testARMArch("armv7ve", "generic", "v7ve", + ARMBuildAttrs::CPUArch::v7)); + EXPECT_TRUE( testARMArch("armv7-r", "cortex-r4", "v7r", ARMBuildAttrs::CPUArch::v7)); EXPECT_TRUE( @@ -502,12 +505,12 @@ TEST(TargetParserTest, ARMparseHWDiv) { TEST(TargetParserTest, ARMparseArchEndianAndISA) { const char *Arch[] = { - "v2", "v2a", "v3", "v3m", "v4", "v4t", "v5", "v5t", - "v5e", "v5te", "v5tej", "v6", "v6j", "v6k", "v6hl", "v6t2", - "v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a", - "v7", "v7a", "v7hl", "v7l", "v7-r", "v7r", "v7-m", "v7m", - "v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a", "v8.1-a", - "v8.1a", "v8.2-a", "v8.2a", "v8-r"}; + "v2", "v2a", "v3", "v3m", "v4", "v4t", "v5", "v5t", + "v5e", "v5te", "v5tej", "v6", "v6j", "v6k", "v6hl", "v6t2", + "v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a", + "v7", "v7a", "v7ve", "v7hl", "v7l", "v7-r", "v7r", "v7-m", + "v7m", "v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a", + "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8-r"}; for (unsigned i = 0; i < array_lengthof(Arch); i++) { std::string arm_1 = "armeb" + (std::string)(Arch[i]); @@ -559,6 +562,7 @@ TEST(TargetParserTest, ARMparseArchProfile) { EXPECT_EQ(ARM::PK_R, ARM::parseArchProfile(ARMArch[i])); continue; case ARM::AK_ARMV7A: + case ARM::AK_ARMV7VE: case ARM::AK_ARMV7K: case ARM::AK_ARMV8A: case ARM::AK_ARMV8_1A: |
