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| author | Craig Topper <craig.topper@intel.com> | 2019-09-06 21:49:01 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-06 21:49:01 +0000 |
| commit | 03936cb0f942a9a78220ffc25d2849f29a1c4511 (patch) | |
| tree | 866728324bf9c8d53d9763f0899d48199eb13d63 /llvm/unittests/ExecutionEngine/Orc/RPCUtilsTest.cpp | |
| parent | a31112e3576a5ae0b0959dd20a66d3689d8d9014 (diff) | |
| download | bcm5719-llvm-03936cb0f942a9a78220ffc25d2849f29a1c4511.tar.gz bcm5719-llvm-03936cb0f942a9a78220ffc25d2849f29a1c4511.zip | |
[X86] Add a AVX512VBMI command line to min-legal-vector-width.ll. Always enable fast-variable-shuffle
Trying to minimize the features we need to manipulate when this
is updated for D67259.
The VBMI is interesting because it enables some improved combining
for truncates.
I enabled fast-variable-shuffle because all the CPUs we're going
to add implicitly enable it. So they can share check lines.
llvm-svn: 371261
Diffstat (limited to 'llvm/unittests/ExecutionEngine/Orc/RPCUtilsTest.cpp')
0 files changed, 0 insertions, 0 deletions
